公开(公告)号：US20170200621A1

公开(公告)日：2017-07-13

申请号：US15469284

申请日：2017-03-24

Applicant: Intel Corporation

Inventor： Omkar G. KARHADE ,  Nitin A. DESHPANDE, JR. ,  Aditya Sundoctor VAIDYA ,  Nachiket R. RARAVIKAR ,  Eric J. LI

IPC: H01L21/56 ,  H01L21/768 ,  H01L21/78

Abstract: Embodiments describe a semiconductor package that includes a substrate, a die bonded to the substrate, and a solder paste overmold layer formed over a top surface of the die. In an embodiment, the solder paste comprises a high-melting point metal, a solder matrix, intermetallic compounds and a polymer. The overmold layer has a high elastic modulus, a coefficient of thermal expansion similar to the substrate, and reduces the warpage of the package. In an embodiment, interconnects of a semiconductor package are formed with a no-slump solder paste that includes vents. Vents may be formed through a conductive network formed by the high-melting point metal, solder matrix and intermetallic compounds. In an embodiment, vents provide a path through the interconnect that allows for moisture outgassing. In an embodiment, a mold layer may be mechanically anchored to the interconnects by the vents, thereby providing improved mechanical continuity to the mold layer.