公开(公告)号：US10936312B2

公开(公告)日：2021-03-02

申请号：US15947622

申请日：2018-04-06

Applicant: Intel Corporation

Inventor： Edwin Jan Van Dalen ,  Alexander Augusteijn ,  Martinus C. Wezelenburg ,  Steven Roos

IPC: G06F9/30

Abstract: A processor includes a decode unit to decode a packed data alignment plus compute instruction. The instruction is to indicate a first set of one or more source packed data operands that is to include first data elements, a second set of one or more source packed data operands that is to include second data elements, at least one data element offset. An execution unit, in response to the instruction, is to store a result packed data operand that is to include result data elements that each have a value of an operation performed with a pair of a data element of the first set of source packed data operands and a data element of the second set of source packed data operands. The execution unit is to apply the at least one data element offset to at least a corresponding one of the first and second sets of source packed data operands. The at least one data element offset is to counteract any lack of correspondence between the data elements of each pair in the first and second sets of source packed data operands.

公开(公告)号：US20160357563A1

公开(公告)日：2016-12-08

申请号：US14728693

申请日：2015-06-02

Applicant: Intel Corporation

Inventor： Edwin Jan Van Dalen ,  Alexander Augusteijn ,  Martinus C. Wezelenburg ,  Steven Roos

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30032 ,  G06F9/3016

Abstract: A processor includes a decode unit to decode a packed data alignment plus compute instruction. The instruction is to indicate a first set of one or more source packed data operands that is to include first data elements, a second set of one or more source packed data operands that is to include second data elements, at least one data element offset. An execution unit, in response to the instruction, is to store a result packed data operand that is to include result data elements that each have a value of an operation performed with a pair of a data element of the first set of source packed data operands and a data element of the second set of source packed data operands. The execution unit is to apply the at least one data element offset to at least a corresponding one of the first and second sets of source packed data operands. The at least one data element offset is to counteract any lack of correspondence between the data elements of each pair in the first and second sets of source packed data operands.

Abstract translation: 处理器包括用于解码打包数据对齐加计算指令的解码单元。 指令是指示要包括第一数据元素的一个或多个源打包数据操作数的第一组，包括第二数据元素的一个或多个源压缩数据操作数的第二组，至少一个数据元偏移量。 响应于该指令，执行单元将存储结果打包数据操作数，该结果打包数据操作数包括结果数据元素，每个结果数据元素具有使用第一组源打包数据操作数的一对数据元素执行的操作值 以及第二组源打包数据操作数的数据元素。 所述执行单元将所述至少一个数据元素偏移应用于所述第一和第二组源打包数据操作数中的至少相应的一个。 所述至少一个数据元素偏移是抵消在第一和第二组源打包数据操作数中的每对数据元素之间的任何对应关系的缺乏。

公开(公告)号：US10001995B2

公开(公告)日：2018-06-19

申请号：US14728693

申请日：2015-06-02

Applicant: Intel Corporation

Inventor： Edwin Jan Van Dalen ,  Alexander Augusteijn ,  Martinus C. Wezelenburg ,  Steven Roos

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30032 ,  G06F9/3016

Abstract: A processor includes a decode unit to decode a packed data alignment plus compute instruction. The instruction is to indicate a first set of one or more source packed data operands that is to include first data elements, a second set of one or more source packed data operands that is to include second data elements, at least one data element offset. An execution unit, in response to the instruction, is to store a result packed data operand that is to include result data elements that each have a value of an operation performed with a pair of a data element of the first set of source packed data operands and a data element of the second set of source packed data operands. The execution unit is to apply the at least one data element offset to at least a corresponding one of the first and second sets of source packed data operands. The at least one data element offset is to counteract any lack of correspondence between the data elements of each pair in the first and second sets of source packed data operands.