公开(公告)号：US20160261807A1

公开(公告)日：2016-09-08

申请号：US14635614

申请日：2015-03-02

Applicant: Intel Corporation

Inventor： Kalpana Seshadrinathan ,  Ramkumar Narayanswamy ,  Alexander N. Zaplatin ,  Joseph A. Hook ,  Sheldon L. Sun ,  Igor V. Kozintsev

IPC: H04N5/247 ,  H04N5/232

CPC classification number: H04N5/247 ,  H04N5/2258 ,  H04N5/232 ,  H04N5/23206 ,  H04N5/23229

Abstract: Techniques for image synchronization are described herein. The techniques may include a device having logic, at least partially including hardware logic, to implement modules. The modules may include a first sync pulse module to issue a first sync pulse after a first sync pulse offset period to a first imaging sensor. The modules may also include a second sync pulse module to issue a second sync pulse parallel to the first sync pulse after a second sync pulse offset period to a second imaging sensor.

Abstract translation: 本文描述了用于图像同步的技术。 这些技术可以包括具有至少部分地包括硬件逻辑的逻辑以实现模块的设备。 模块可以包括第一同步脉冲模块，以在第一同步脉冲偏移周期之后向第一成像传感器发出第一同步脉冲。 模块还可以包括第二同步脉冲模块，以在与第二成像传感器的第二同步脉冲偏移周期之后发出平行于第一同步脉冲的第二同步脉冲。

公开(公告)号：US09819875B2

公开(公告)日：2017-11-14

申请号：US14635614

申请日：2015-03-02

Applicant: Intel Corporation

Inventor： Kalpana Seshadrinathan ,  Ramkumar Narayanswamy ,  Alexander N. Zaplatin ,  Joseph A. Hook ,  Sheldon L. Sun ,  Igor V. Kozintsev

IPC: H04N5/247 ,  H04N5/232 ,  H04N5/225

CPC classification number: H04N5/247 ,  H04N5/2258 ,  H04N5/232 ,  H04N5/23206 ,  H04N5/23229

Abstract: Techniques for image synchronization are described herein. The techniques may include a device having logic, at least partially including hardware logic, to implement modules. The modules may include a first sync pulse module to issue a first sync pulse after a first sync pulse offset period to a first imaging sensor. The modules may also include a second sync pulse module to issue a second sync pulse parallel to the first sync pulse after a second sync pulse offset period to a second imaging sensor.