公开(公告)号：US20190004770A1

公开(公告)日：2019-01-03

申请号：US15637453

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Sudhir K. Satpathy ,  Raghavan Kumar ,  Arvind Singh ,  Vikram B. Suresh ,  Sanu K. Mathew

IPC: G06F7/72 ,  H04L9/32

Abstract: In one embodiment, an apparatus comprises a multiplier circuit to: identify a point multiply operation to be performed by the multiplier circuit, wherein the point multiply operation comprises point multiplication of a first plurality of operands; identify a point add operation associated with the point multiply operation, wherein the point add operation comprises point addition of a second plurality of operands, wherein the second plurality of operands comprises a first point and a second point, and wherein the first point and the second point are associated with a first coordinate system; convert the second point from the first coordinate system to a second coordinate system; perform the point add operation based on the first point associated with the first coordinate system and the second point associated with the second coordinate system; and perform the point multiply operation based on a result of the point add operation.