公开(公告)号：US20190265974A1

公开(公告)日：2019-08-29

申请号：US15903549

申请日：2018-02-23

Applicant: Intel Corporation

Inventor： BUQI CHENG ,  WEI-YU CHEN ,  GUEI-YUAN LUEH ,  CHANDRA GURRAM ,  SUBRAMANIAM MAIYURAN

IPC: G06F9/30 ,  G06F9/48 ,  G06T1/20

Abstract: Mechanisms for reducing register bank conflicts based on software hint and hardware thread switch are disclosed. In some embodiments, an apparatus for thread switching includes a graphics processing unit (GPU) that includes a plurality of register banks to store operands that are assigned at least partially to avoid register bank conflicts. A decoding circuitry checks a thread switching field of a first instruction to be executed by a first thread. The GPU performs a thread switch mechanism to cause a second instruction to be executed by a second thread when the thread switching field of the first instruction is set.

公开(公告)号：US20220179655A1

公开(公告)日：2022-06-09

申请号：US17502492

申请日：2021-10-15

Applicant: Intel Corporation

Inventor： BUQI CHENG ,  WEI-YU CHEN ,  GUEI-YUAN LUEH ,  CHANDRA GURRAM ,  SUBRAMANIAM MAIYURAN

IPC: G06F9/38 ,  G06F9/30 ,  G06F8/41

Abstract: Mechanisms for reducing register bank conflicts based on software hint and hardware thread switch are disclosed. In some embodiments, an apparatus for thread switching includes a graphics processing unit (GPU) that includes a plurality of register banks to store operands that are assigned at least partially to avoid register bank conflicts. A decoding circuitry checks a thread switching field of a first instruction to be executed by a first thread. The GPU performs a thread switch mechanism to cause a second instruction to be executed by a second thread when the thread switching field of the first instruction is set.