公开(公告)号：US09543244B2

公开(公告)日：2017-01-10

申请号：US14543838

申请日：2014-11-17

Applicant: Intel Corporation

Inventor： Chung Peng Jackson Kong ,  Chang-Tsung Fu ,  Telesphor Kamgaing ,  Chan Kim Lee ,  Ping Ping Ooi

IPC: H01L23/522 ,  H01L23/52 ,  H01L23/498 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/528 ,  H01L2224/16

Abstract: “Hybrid” transmission line circuits employing multiple interconnect levels for the propagation, or return, of a single signal line across a package length are described. In package transmission line circuit embodiments, a signal line employs co-located traces in two different interconnect levels that are electrically coupled together. In further embodiments, a reference plane is provided above, below or co-planar with at least one of the co-locate traces. In embodiments, a balanced signal line pair includes first and second co-located traces in two adjacent interconnect levels as a propagation signal line and third and fourth co-located traces in the two adjacent interconnect levels as a return signal line with a ground plane co-planar with, and/or above and/or below the two adjacent interconnect levels.

Abstract translation: 描述了采用多个互连级别以跨越封装长度传播或返回单条信号线的“混合”传输线路电路。 在封装传输线路电路实施例中，信号线在电耦合在一起的两个不同的互连级别中使用共同定位的迹线。 在另外的实施例中，参考平面被提供在至少一个共定位轨迹的上方，下方或共面上。 在实施例中，平衡信号线对包括作为传播信号线的两个相邻互连级别中的第一和第二同位置迹线，以及在两个相邻互连级别中的第三和第四同位序列作为具有接地平面Co 平面，和/或上方和/或下方两个相邻互连层。