公开(公告)号：US20210349966A1

公开(公告)日：2021-11-11

申请号：US16913800

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： SUBRAMANIAM MAIYURAN ,  JORGE PARRA ,  SUPRATIM PAL ,  ASHUTOSH GARG ,  SHUBRA MARWAHA ,  CHANDRA GURRAM ,  DARIN STARKEY ,  DURGESH BORKAR ,  VARGHESE GEORGE

IPC: G06F17/16 ,  G06F9/30 ,  G06F15/80

Abstract: Described herein is an accelerator device including a host interface, a fabric interconnect coupled with the host interface, and one or more hardware tiles coupled with the fabric interconnect, the one or more hardware tiles including sparse matrix multiply acceleration hardware including a systolic array with feedback inputs.

公开(公告)号：US20220156343A1

公开(公告)日：2022-05-19

申请号：US17527882

申请日：2021-11-16

Applicant: Intel Corporation

Inventor： SUBRAMANIAM MAIYURAN ,  JORGE PARRA ,  SUPRATIM PAL ,  ASHUTOSH GARG ,  SHUBRA MARWAHA ,  CHANDRA GURRAM ,  DARIN STARKEY ,  DURGESH BORKAR ,  VARGHESE GEORGE

IPC: G06F17/16 ,  G06F15/80 ,  G06F9/30

Abstract: Described herein is an accelerator device including a host interface, a fabric interconnect coupled with the host interface, and one or more hardware tiles coupled with the fabric interconnect, the one or more hardware tiles including sparse matrix multiply acceleration hardware including a systolic array with feedback inputs.

公开(公告)号：US20240427847A1

公开(公告)日：2024-12-26

申请号：US18757003

申请日：2024-06-27

Applicant: Intel Corporation

Inventor： SUBRAMANIAM MAIYURAN ,  JORGE PARRA ,  SUPRATIM PAL ,  ASHUTOSH GARG ,  SHUBRA MARWAHA ,  CHANDRA GURRAM ,  DARIN STARKEY ,  DURGESH BORKAR ,  VARGHESE GEORGE

IPC: G06F17/16 ,  G06F9/30 ,  G06F15/80

Abstract: Described herein is a graphics processor including a plurality of processing clusters coupled with a host interface, each processing cluster comprising a plurality of multiprocessors, the plurality of multiprocessors interconnected via a data interconnect, and each multiprocessor comprising sparse matrix multiply acceleration hardware including a systolic processing array with feedback inputs.

公开(公告)号：US20230281272A1

公开(公告)日：2023-09-07

申请号：US18301386

申请日：2023-04-17

Applicant: Intel Corporation

Inventor： SUBRAMANIAM MAIYURAN ,  JORGE PARRA ,  SUPRATIM PAL ,  ASHUTOSH GARG ,  SHUBRA MARWAHA ,  CHANDRA GURRAM ,  DARIN STARKEY ,  DURGESH BORKAR ,  VARGHESE GEORGE

IPC: G06F17/16 ,  G06F9/30 ,  G06F15/80

CPC classification number: G06F17/16 ,  G06F9/3001 ,  G06F9/30145 ,  G06F15/8046

Abstract: Described herein is a graphics processor including a plurality of processing clusters coupled with a host interface, each processing cluster comprising a plurality of multiprocessors, the plurality of multiprocessors interconnected via a data interconnect, and each multiprocessor comprising sparse matrix multiply acceleration hardware including a systolic processing array with feedback inputs.