公开(公告)号：US11902218B2

公开(公告)日：2024-02-13

申请号：US17808123

申请日：2022-06-22

Applicant: Intel Corporation

Inventor： David Barr ,  Bernard Arambepola

IPC: H04L5/14 ,  H04B3/02 ,  H04B3/32 ,  H04L12/28 ,  H04L65/1101

CPC classification number: H04L5/14 ,  H04B3/02 ,  H04B3/32 ,  H04L12/2801 ,  H04L12/2898 ,  H04L65/1101

Abstract: A head-end equipment associated with a communication system configured to interface with an interference group (IG) composed of two or more modems is disclosed. The head-end equipment comprises a memory configured to store a plurality of instructions; and one or more processors configured to retrieve the plurality of instructions from the memory. In some embodiments, the one or more processors, upon execution of the plurality of instructions from the memory, is configured to generate an advanced warning signal to be provided to one or more modems associated with the IG. In some embodiments, the advanced warning signal comprises an information that a select modem, different from the one or more modems, in the IG will be initiating an upstream communication in a select frequency band, as well as information on a start time and a duration of the upstream communication.

公开(公告)号：US20180287770A1

公开(公告)日：2018-10-04

申请号：US15908360

申请日：2018-02-28

Applicant: Intel Corporation

Inventor： David Barr ,  Bernard Arambepola

IPC: H04L5/14 ,  H04L12/28 ,  H04L29/06

Abstract: A head-end equipment associated with a communication system configured to interface with an interference group (IG) composed of two or more modems is disclosed. The head-end equipment comprises a memory configured to store a plurality of instructions; and one or more processors configured to retrieve the plurality of instructions from the memory. In some embodiments, the one or more processors, upon execution of the plurality of instructions from the memory, is configured to generate an advanced warning signal to be provided to one or more modems associated with the IG. In some embodiments, the advanced warning signal comprises an information that a select modem, different from the one or more modems, in the IG will be initiating an upstream communication in a select frequency band, as well as information on a start time and a duration of the upstream communication.

公开(公告)号：US20200266966A1

公开(公告)日：2020-08-20

申请号：US16866580

申请日：2020-05-05

Applicant: Intel Corporation

Inventor： David Barr ,  Bernard Arambepola

IPC: H04L5/14 ,  H04B3/32 ,  H04B3/02 ,  H04L12/28 ,  H04L29/06

Abstract: A head-end equipment associated with a communication system configured to interface with an interference group (IG) composed of two or more modems is disclosed. The head-end equipment comprises a memory configured to store a plurality of instructions; and one or more processors configured to retrieve the plurality of instructions from the memory. In some embodiments, the one or more processors, upon execution of the plurality of instructions from the memory, is configured to generate an advanced warning signal to be provided to one or more modems associated with the IG. In some embodiments, the advanced warning signal comprises an information that a select modem, different from the one or more modems, in the IG will be initiating an upstream communication in a select frequency band, as well as information on a start time and a duration of the upstream communication.

公开(公告)号：US11411709B2

公开(公告)日：2022-08-09

申请号：US16866580

申请日：2020-05-05

Applicant: Intel Corporation

Inventor： David Barr ,  Bernard Arambepola

IPC: H04L5/14 ,  H04B3/02 ,  H04L29/06 ,  H04B3/32 ,  H04L12/28 ,  H04L65/1101

Abstract: A head-end equipment associated with a communication system configured to interface with an interference group (IG) composed of two or more modems is disclosed. The head-end equipment comprises a memory configured to store a plurality of instructions; and one or more processors configured to retrieve the plurality of instructions from the memory. In some embodiments, the one or more processors, upon execution of the plurality of instructions from the memory, is configured to generate an advanced warning signal to be provided to one or more modems associated with the IG. In some embodiments, the advanced warning signal comprises an information that a select modem, different from the one or more modems, in the IG will be initiating an upstream communication in a select frequency band, as well as information on a start time and a duration of the upstream communication.

公开(公告)号：US10855433B2

公开(公告)日：2020-12-01

申请号：US15908360

申请日：2018-02-28

Applicant: Intel Corporation

Inventor： David Barr ,  Bernard Arambepola

IPC: H04L5/14 ,  H04L12/28 ,  H04L29/06 ,  H04B3/02 ,  H04B3/32

Abstract: A head-end equipment associated with a communication system configured to interface with an interference group (IG) composed of two or more modems is disclosed. The head-end equipment comprises a memory configured to store a plurality of instructions; and one or more processors configured to retrieve the plurality of instructions from the memory. In some embodiments, the one or more processors, upon execution of the plurality of instructions from the memory, is configured to generate an advanced warning signal to be provided to one or more modems associated with the IG. In some embodiments, the advanced warning signal comprises an information that a select modem, different from the one or more modems, in the IG will be initiating an upstream communication in a select frequency band, as well as information on a start time and a duration of the upstream communication.

公开(公告)号：US20190044555A1

公开(公告)日：2019-02-07

申请号：US15978213

申请日：2018-05-14

Applicant: Intel Corporation

Inventor： Thushara Hewavithana ,  Shaul Shulman ,  Noam Tal ,  Boaz Kol ,  Nathan Goichberg ,  David Barr

IPC: H04B1/04 ,  H04B3/20 ,  H04L27/26 ,  H04L5/14

Abstract: A method and apparatus for cancelling self-interference in a cable network implementing full duplex (FDX). A processor in a cable modem may obtain a frequency response of an echo channel for at least one sub-channel in an FDX band and calculate filter coefficients based on the frequency response, and an interference canceller cancels the self-interference in the downstream signal. The interference canceller includes filters in a digital domain to generate an interference cancellation signal from a reference signal. In another example, the processor may obtain frequency responses of an echo channel for all sub-channels in a FDX band, combine the frequency responses for the FDX band, and generate a channel impulse response for the FDX band from the combined frequency response. The interference canceller may then cancel the self-interference in the downstream signal in an analog domain based on the channel impulse response.