公开(公告)号：US11941400B2

公开(公告)日：2024-03-26

申请号：US17672142

申请日：2022-02-15

Applicant: Intel Corporation

Inventor： Adam Herr ,  Derek Gerstmann ,  Justin Gottschlich ,  Mikael Bourges-Sevenier ,  Sridhar Sharma

IPC: G06F9/30 ,  G06F8/30 ,  G06F8/52 ,  G06F8/75 ,  G06F8/76 ,  G06F9/38 ,  G06N3/04

CPC classification number: G06F9/30174 ,  G06F8/31 ,  G06F8/52 ,  G06F8/75 ,  G06F8/76 ,  G06F9/3877 ,  G06N3/04

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for intentional programming for heterogeneous systems. An example non-transitory computer readable storage medium includes instructions that, when executed, cause processor circuitry to at least identify a first code block having a first algorithmic purpose based on a second code block having a second algorithmic purpose, the second algorithmic purpose corresponding to the first algorithmic purpose, translate the first code block into executable domain specific language code, and output the executable domain specific language code.

公开(公告)号：US20240329997A1

公开(公告)日：2024-10-03

申请号：US18434426

申请日：2024-02-06

Applicant: Intel Corporation

Inventor： Adam Herr ,  Derek Gerstmann ,  Justin Gottschlich ,  Mikael Bourges-Sevenier ,  Sridhar Sharma

IPC: G06F9/30 ,  G06F8/30 ,  G06F8/52 ,  G06F8/75 ,  G06F8/76 ,  G06F9/38 ,  G06N3/04

CPC classification number: G06F9/30174 ,  G06F8/31 ,  G06F8/52 ,  G06F8/75 ,  G06F8/76 ,  G06F9/3877 ,  G06N3/04

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for intentional programming for heterogeneous systems. An example apparatus includes a code lifter to identify annotated code corresponding to an algorithm to be executed on the heterogeneous system based on an identifier being associated with the annotated code, and convert the annotated code in the first representation to intermediate code in a second representation by identifying the intermediate code as having a first algorithmic intent that corresponds to a second algorithmic intent of the annotated code, a domain specific language (DSL) generator to translate the intermediate code in the second representation to DSL code in a third representation when the first algorithmic intent matches the second algorithmic intent, the third representation corresponding to a DSL representation, and a code replacer to invoke a compiler to generate an executable including variant binaries based on the DSL code.

公开(公告)号：US20190317880A1

公开(公告)日：2019-10-17

申请号：US16455486

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Adam Herr ,  Sridhar Sharma ,  Mikael Bourges-Sevenier ,  Derek Gerstmann ,  Justin Gottschlich

IPC: G06F11/36 ,  G06N20/00

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed improve runtime performance of software executing on a heterogeneous system. An example apparatus includes a feedback interface to collect a performance characteristic of the heterogeneous system associated with a compiled version of a block of code at a first runtime, the compiled version executed according to a function designating successful execution of the compiled version on the heterogeneous system, the heterogeneous system including a first processing element and a second processing element different than the first processing element; a performance analyzer to determine a performance delta based on the performance characteristic and the function; and a machine learning modeler to, prior to a second runtime, adjust a cost model of the first processing element based on the performance delta, the adjusted cost model to cause a reduction in the performance delta to improve runtime performance of the heterogeneous system.

公开(公告)号：US10908884B2

公开(公告)日：2021-02-02

申请号：US16455379

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Adam Herr ,  Derek Gerstmann ,  Justin Gottschlich ,  Mikael Bourges-Sevenier ,  Sridhar Sharma

IPC: G06F9/44 ,  G06F8/41 ,  G06N3/08 ,  G06F8/54 ,  G06F9/48

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for runtime scheduling of software executing on a heterogeneous system. An example apparatus includes in response to a variant compiler to generate a representation of an algorithm in a domain-specific language (DSL), a compilation auto-scheduler to generate a schedule based on configurations for processing elements of the heterogeneous system, the processing elements including at least a first and a second processing element, the variant compiler to compile variant binaries based on the schedule, each of the variant binaries associated with the algorithm in the DSL, the variant binaries including a first variant binary corresponding to the first processing element and a second variant binary corresponding to the second processing element, and an application compiler to generate a fat binary including a runtime scheduler to select one or more of the variant binaries to execute a workload based on the schedule.

公开(公告)号：US20190325314A1

公开(公告)日：2019-10-24

申请号：US16456863

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Mikael Bourges-Sevenier ,  Adam Herr ,  Sridhar Sharma ,  Derek Gerstmann ,  Todd Anderson ,  Justin Gottschlich

IPC: G06N3/08 ,  G06F17/16

Abstract: Methods, apparatus, systems and articles of manufacture to optimize execution of a machine learning model are disclosed. An example apparatus includes a quantizer to quantize a layer of a model based on an execution constraint, the layer of the model represented by a matrix. A packer is to pack the quantized layer of the matrix to create a packed layer represented by a packed matrix, the packed matrix having non-zero values of the matrix grouped together along at least one of a row or a column of the matrix. A blocker is to block the packed layer into a blocked layer by dividing the non-zero values in the packed matrix into blocks. A fuser is to fuse the blocked layer into a pipeline. A packager is to package the pipeline into a binary.

公开(公告)号：US20190317740A1

公开(公告)日：2019-10-17

申请号：US16455379

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Adam Herr ,  Derek Gerstmann ,  Justin Gottschlich ,  Mikael Bourges-Sevenier ,  Sridhar Sharma

IPC: G06F8/41 ,  G06F8/54 ,  G06N3/08

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for runtime scheduling of software executing on a heterogeneous system. An example apparatus includes in response to a variant compiler to generate a representation of an algorithm in a domain-specific language (DSL), a compilation auto-scheduler to generate a schedule based on configurations for processing elements of the heterogeneous system, the processing elements including at least a first and a second processing element, the variant compiler to compile variant binaries based on the schedule, each of the variant binaries associated with the algorithm in the DSL, the variant binaries including a first variant binary corresponding to the first processing element and a second variant binary corresponding to the second processing element, and an application compiler to generate a fat binary including a runtime scheduler to select one or more of the variant binaries to execute a workload based on the schedule.

公开(公告)号：US11507838B2

公开(公告)日：2022-11-22

申请号：US16456863

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Mikael Bourges-Sevenier ,  Adam Herr ,  Sridhar Sharma ,  Derek Gerstmann ,  Todd Anderson ,  Justin Gottschlich

IPC: G06N3/08 ,  G06F17/16

Abstract: Methods, apparatus, systems and articles of manufacture to optimize execution of a machine learning model are disclosed. An example apparatus includes a quantizer to quantize a layer of a model based on an execution constraint, the layer of the model represented by a matrix. A packer is to pack the quantized layer of the matrix to create a packed layer represented by a packed matrix, the packed matrix having non-zero values of the matrix grouped together along at least one of a row or a column of the matrix. A blocker is to block the packed layer into a blocked layer by dividing the non-zero values in the packed matrix into blocks. A fuser is to fuse the blocked layer into a pipeline. A packager is to package the pipeline into a binary.

公开(公告)号：US20220171626A1

公开(公告)日：2022-06-02

申请号：US17672142

申请日：2022-02-15

Applicant: Intel Corporation

Inventor： Adam Herr ,  Derek Gerstmann ,  Justin Gottschlich ,  Mikael Bourges-Sevenier ,  Sridhar Sharma

IPC: G06F9/30 ,  G06F8/52 ,  G06F8/30 ,  G06F8/75 ,  G06N3/04 ,  G06F8/76 ,  G06F9/38

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for intentional programming for heterogeneous systems. An example non-transitory computer readable storage medium includes instructions that, when executed, cause processor circuitry to at least identify a first code block having a first algorithmic purpose based on a second code block having a second algorithmic purpose, the second algorithmic purpose corresponding to the first algorithmic purpose, translate the first code block into executable domain specific language code, and output the executable domain specific language code.

公开(公告)号：US11269639B2

公开(公告)日：2022-03-08

申请号：US16455388

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Adam Herr ,  Derek Gerstmann ,  Justin Gottschlich ,  Mikael Bourges-Sevenier ,  Sridhar Sharma

IPC: G06F9/30 ,  G06F8/30 ,  G06F8/52 ,  G06F8/76 ,  G06F8/75 ,  G06N3/04 ,  G06F9/38

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for intentional programming for heterogeneous systems. An example apparatus includes a code lifter to identify annotated code corresponding to an algorithm to be executed on the heterogeneous system based on an identifier being associated with the annotated code, and convert the annotated code in the first representation to intermediate code in a second representation by identifying the intermediate code as having a first algorithmic intent that corresponds to a second algorithmic intent of the annotated code, a domain specific language (DSL) generator to translate the intermediate code in the second representation to DSL code in a third representation when the first algorithmic intent matches the second algorithmic intent, the third representation corresponding to a DSL representation, and a code replacer to invoke a compiler to generate an executable including variant binaries based on the DSL code.

公开(公告)号：US20190324755A1

公开(公告)日：2019-10-24

申请号：US16455388

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Adam Herr ,  Derek Gerstmann ,  Justin Gottschlich ,  Mikael Bourges-Sevenier ,  Sridhar Sharma

IPC: G06F9/30 ,  G06F8/52 ,  G06F8/30 ,  G06F9/38 ,  G06N3/04 ,  G06F8/76 ,  G06F8/75

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for intentional programming for heterogeneous systems. An example apparatus includes a code lifter to identify annotated code corresponding to an algorithm to be executed on the heterogeneous system based on an identifier being associated with the annotated code, and convert the annotated code in the first representation to intermediate code in a second representation by identifying the intermediate code as having a first algorithmic intent that corresponds to a second algorithmic intent of the annotated code, a domain specific language (DSL) generator to translate the intermediate code in the second representation to DSL code in a third representation when the first algorithmic intent matches the second algorithmic intent, the third representation corresponding to a DSL representation, and a code replacer to invoke a compiler to generate an executable including variant binaries based on the DSL code.