公开(公告)号：US20220147800A1

公开(公告)日：2022-05-12

申请号：US17526628

申请日：2021-11-15

Applicant: Intel Corporation

Inventor： Julio ZAMORA ESQUIVEL ,  Hector CORDOURIER MARURI ,  Jose CAMACHO PEREZ ,  Paulo LOPEZ MEYER ,  Jesus Adan CRUZ VARGAS

IPC: G06N3/04 ,  G06N3/08

Abstract: Methods and apparatuses for implementing a neural network using symmetric tensors. In embodiments, a system may include a higher order neural network with a plurality of layers that includes an input layer, one or more hidden layers, and an output layer. Each of the input layer, the one or more hidden layers, and the output layer includes a plurality of neurons, where the plurality of neurons includes at least first order neurons and second order neurons, and where inputs at a second order neuron are combined using a symmetric tensor.

公开(公告)号：US20230098162A1

公开(公告)日：2023-03-30

申请号：US17932318

申请日：2022-09-15

Applicant: Intel Corporation

Inventor： Assaf GUREVITZ ,  Shahrnaz AZIZI ,  Amir RUBIN ,  Eduardo ALBAN ,  Hector CORDOURIER MARURI ,  Janardhan KORATIKERE NARAYAN ,  Jie GAO ,  Jose Rodrigo CAMACHO PEREZ ,  Shlomi VITURI ,  Vinod KRISTEM ,  Ivan SIMOES GASPAR ,  Amer AL-BAIDHANI

IPC: H04B1/10 ,  H04B17/345

Abstract: A method and apparatus to estimate and mitigate platform noise incurred at a wireless device coupled to the platform. A computing device includes a platform including a first processor, a wireless device coupled to the platform, the wireless device including a second processor, and a plurality of antennas coupled to the wireless device. At least one of the first processor or the second processor is configured to determine characteristics of a platform noise incurred at the wireless device in real-time due to utilization of circuitries and processing components on the platform and implement an adaptive real-time and application/context-aware measure to mitigate the platform noise based on the determined characteristics of the platform noise.

公开(公告)号：US20190042921A1

公开(公告)日：2019-02-07

申请号：US15924947

申请日：2018-03-19

Applicant: Intel Corporation

Inventor： Julio ZAMORA ESQUIVEL ,  Hector CORDOURIER MARURI ,  Jose CAMACHO PEREZ ,  Paulo LOPEZ MEYER ,  Jesus Adan CRUZ VARGAS

IPC: G06N3/04 ,  G06N3/08

Abstract: Methods and apparatuses for implementing a neural network using symmetric tensors. In embodiments, a system may include a higher order neural network with a plurality of layers that includes an input layer, one or more hidden layers, and an output layer. Each of the input layer, the one or more hidden layers, and the output layer includes a plurality of neurons, where the plurality of neurons includes at least first order neurons and second order neurons, and where inputs at a second order neuron are combined using a symmetric tensor.