公开(公告)号：US10374793B2

公开(公告)日：2019-08-06

申请号：US15374700

申请日：2016-12-09

Applicant: Intel Corporation

Inventor： Himanshu Kaul ,  Sanu Mathew ,  Mark Anders ,  Jesse Walker ,  Jason Sandri

IPC: H04L9/06 ,  G06F12/14 ,  G06F17/50

Abstract: An instruction and logic for a Simon-based hashing for validation are described. In one embodiment, a processor comprises: a memory the memory to store a plurality of values; and a hash circuit comprising a Simon cipher circuit operable to receive the plurality of values from the memory, to apply a Simon cipher, and to generate an output for each of the plurality of values; and circuitry coupled to the Simon cipher circuit to combine outputs from the Simon cipher circuit for each value of the plurality of values into a hash digest that is indicative of whether the values in the memory are valid.