公开(公告)号：US20240332172A1

公开(公告)日：2024-10-03

申请号：US18129872

申请日：2023-04-02

Applicant: Intel Corporation

Inventor： Ehren MANNEBACH ,  Shaun MILLS ,  Joseph D’SILVA ,  Mauro J. KOBRINSKY ,  Makram ABD El QADER

IPC: H01L23/528 ,  H01L29/423

CPC classification number: H01L23/528 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/785

Abstract: Integrated circuit structures having backside contact widening are described. In an example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate stack is over the plurality of horizontally stacked nanowires. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A conductive gate contact is vertically beneath and in contact with a bottom of the gate stack. The conductive gate contact is in a cavity in an isolation layer, the cavity extending beyond the gate stack in a direction parallel with the epitaxial source or drain structure, and the cavity confined to the gate stack in a direction toward the epitaxial source or drain structure.