公开(公告)号：US20230100873A1

公开(公告)日：2023-03-30

申请号：US18061954

申请日：2022-12-05

Applicant: Intel Corporation

Inventor： Enrico Galli ,  Andrew S. Brown ,  Mingqiu Sun ,  Petr Penzin

IPC: G06F9/50 ,  G06F9/30 ,  G06F11/07

Abstract: An apparatus includes a first processor to be communicatively coupled to a main memory having instructions stored therein. The first processor is to execute the instructions to assign a first tag to a plurality of granules in a first portion of memory allocated for an offloaded function invoked by a module running on a second processor, detect an exception raised for a tag check failure for a memory access operation based on a first memory address in the first portion of the memory, and update a modified address list to include information associated with the first memory address. The instructions are executed further to synchronize, based on the modified address list, a second portion of the memory allocated to the module with the first portion of the memory.