公开(公告)号：US20190164818A1

公开(公告)日：2019-05-30

申请号：US15859417

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Andrew W. YEOH ,  Ruth BRAIN ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a plurality of conductive interconnect lines in and spaced apart by an inter-layer dielectric (ILD) layer above a substrate. Individual ones of the plurality of conductive interconnect lines have an upper surface below an upper surface of the ILD layer. An etch-stop layer is on and conformal with the ILD layer and the plurality of conductive interconnect lines, the etch-stop layer having a non-planar upper surface with an uppermost portion of the non-planar upper surface over the ILD layer and a lowermost portion of the non-planar upper surface over the plurality of conductive interconnect lines.

公开(公告)号：US20200027781A1

公开(公告)日：2020-01-23

申请号：US16509398

申请日：2019-07-11

Applicant: Intel Corporation

Inventor： Andrew W. YEOH ,  Ruth BRAIN ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a plurality of conductive interconnect lines in and spaced apart by an inter-layer dielectric (ILD) layer above a substrate. Individual ones of the plurality of conductive interconnect lines have an upper surface below an upper surface of the ILD layer. An etch-stop layer is on and conformal with the ILD layer and the plurality of conductive interconnect lines, the etch-stop layer having a non-planar upper surface with an uppermost portion of the non-planar upper surface over the ILD layer and a lowermost portion of the non-planar upper surface over the plurality of conductive interconnect lines.