公开(公告)号：US20200310978A1

公开(公告)日：2020-10-01

申请号：US16367103

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： SCOTT DION RODGERS ,  ROBERT S. CHAPPELL ,  BARRY E. HUNTLEY

IPC: G06F12/1009 ,  G06F12/1027 ,  G06F12/14

Abstract: An apparatus and method for managing different page tables for different privilege levels. For example, one embodiment of a processor comprises: a first control register to store a first base address associated with program code executed at a first privilege level; a second control register to store a second base address associated with program code executed at a second privilege level lower than the first privilege level; and address translation circuitry to identify a first base translation table using the first base address responsive to a first address translation request originating from the program code executed at the first privilege level and to identify a second base translation table using the second base address responsive to a second address translation request originating from the program code executed at the second privilege level.