公开(公告)号：US20210096867A1

公开(公告)日：2021-04-01

申请号：US16586715

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Nir Tell ,  Shahar Sandor ,  Amotz Yagev ,  Michael Hermnoy ,  Sagie Yakov Goldenberg ,  Lihu Rappoport

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/54

Abstract: A system is provided that includes an instruction buffer that stores bytes representative of one or more macroinstructions and instruction length decoder circuitry. The instruction length decoder circuitry includes a non-sequential first multiplexer circuitry having first input lines receiving a first input data representative of a speculative length of a first macroinstruction of the macroinstructions, and first selector that selects from the first input lines via a one-hot selector vector. The instruction length decoder circuitry also includes a first output line communicatively coupled to second selector, wherein the first output line causes the selector to select from a second input data representative of a first location of a first ending byte for the first macroinstruction with respect to a value x. The first multiplexer circuitry and the second selector may output start and end byte locations for the macroinstructions.

公开(公告)号：US11086627B2

公开(公告)日：2021-08-10

申请号：US16586715

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Nir Tell ,  Shahar Sandor ,  Amotz Yagev ,  Michael Hermony ,  Sagie Yakov Goldenberg ,  Lihu Rappoport

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/54

Abstract: A system is provided that includes an instruction buffer that stores bytes representative of one or more macroinstructions and instruction length decoder circuitry. The instruction length decoder circuitry includes a non-sequential first multiplexer circuitry having first input lines receiving a first input data representative of a speculative length of a first macroinstruction of the macroinstructions, and first selector that selects from the first input lines via a one-hot selector vector. The instruction length decoder circuitry also includes a first output line communicatively coupled to second selector, wherein the first output line causes the selector to select from a second input data representative of a first location of a first ending byte for the first macroinstruction with respect to a value x. The first multiplexer circuitry and the second selector may output start and end byte locations for the macroinstructions.