公开(公告)号：US20190131437A1

公开(公告)日：2019-05-02

申请号：US16095655

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Van Hoang LE ,  Gilbert William DEWEY ,  Marko RADOSAVLJEVIC ,  Rafael RIOS ,  Jack T. KAVALIEROS

IPC: H01L29/66 ,  H01L27/12 ,  H01L29/78 ,  H01L29/06 ,  H01L29/24

Abstract: Integrated circuit dies having multi-gate, non-planar transistors built into a back-end-of-line portion of the die are described. In an example, non-planar transistors include an amorphous oxide semiconductor (AOS) channel extending between a source module and a drain module. A gate module may extend around the AOS channel to control electrical current flow between the source module and the drain module. The AOS channel may include an AOS layer having indium gallium zinc oxide.