DEBUGGING TRANSLATION BLOCK AND DEBUGGING ARCHITECTURE

    公开(公告)号:US20180328986A1

    公开(公告)日:2018-11-15

    申请号:US15591161

    申请日:2017-05-10

    Abstract: An electronic device includes one or more integrated circuits, a debugging translation block, and a bus connected to the one or more integrated circuits and the debugging translation block, the bus configured to provide a connection to one or more external devices, wherein the debugging translation block is configured to receive debugging commands from a testing host device via the bus, convert the debugging commands into debugging input data, and provide the debugging input data to a debugging state machine of a first integrated circuit of the one or more integrated circuits.

    Debugging translation block and debugging architecture

    公开(公告)号:US10474515B2

    公开(公告)日:2019-11-12

    申请号:US15591161

    申请日:2017-05-10

    Abstract: An electronic device includes one or more integrated circuits, a debugging translation block, and a bus connected to the one or more integrated circuits and the debugging translation block, the bus configured to provide a connection to one or more external devices, wherein the debugging translation block is configured to receive debugging commands from a testing host device via the bus, convert the debugging commands into debugging input data, and provide the debugging input data to a debugging state machine of a first integrated circuit of the one or more integrated circuits.

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