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公开(公告)号:US11526360B2
公开(公告)日:2022-12-13
申请号:US16196151
申请日:2018-11-20
发明人: Naga P. Gorti , Dave S. Levitan
IPC分类号: G06F9/38
摘要: A processor comprising a processor pipeline comprising one or more execution units configured to execute branch instructions, a branch predictor associated with the processor pipeline and configured to predict a branch instruction prediction outcome, and the branch prediction unit. The branch predictor is turned off to save power and avoid miss-predictions when the branch predictor and/or branch prediction unit accuracy is lower than expected.