公开(公告)号：US20160163704A1

公开(公告)日：2016-06-09

申请号：US14958078

申请日：2015-12-03

Applicant: JAEHOON LEE

Inventor： JAEHOON LEE

IPC: H01L27/092 ,  H01L29/778 ,  H01L29/10

CPC classification number: H01L27/0922 ,  H01L21/8258 ,  H01L29/1054 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device is provided as follows. A first buffer layer is disposed on a substrate including NMOS and PMOS regions. A first drain and a first source are disposed on the first buffer layer and have heterogeneous structures. A first channel is disposed between the first drain and the first source. A first gate electrode is disposed on the first channel. A second drain and a second source are disposed on the first buffer layer. A second channel is disposed between the second drain and the second source. The second channel includes a different material from the first channel. A second gate electrode is disposed on the second channel. The first drain, the first source, the first channel and the first gate electrode are disposed in the NMOS region. The second drain, the second source, the second channel and the second gate electrode are disposed in the PMOS region.

Abstract translation: 如下提供半导体器件。 第一缓冲层设置在包括NMOS和PMOS区的衬底上。 第一漏极和第一源极设置在第一缓冲层上并且具有异质结构。 第一通道设置在第一漏极和第一源极之间。 第一栅电极设置在第一通道上。 第二漏极和第二源极设置在第一缓冲层上。 第二通道设置在第二漏极和第二源极之间。 第二通道包括与第一通道不同的材料。 第二栅电极设置在第二通道上。 第一漏极，第一源极，第一沟道和第一栅电极设置在NMOS区域中。 第二漏极，第二源极，第二沟道和第二栅极设置在PMOS区域中。

公开(公告)号：US20160163788A1

公开(公告)日：2016-06-09

申请号：US14958146

申请日：2015-12-03

Applicant: JAEHOON LEE

Inventor： JAEHOON LEE

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L27/092

CPC classification number: H01L29/0615 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/1054 ,  H01L29/16

Abstract: A semiconductor device is provided as follows. A substrate includes an NMOS region and a PMOS region. A first trench and a second trench are disposed in the NMOS region. A first buffer layer is disposed in the first trench and the second trench. A stressor is disposed in the first trench and the second trench and disposed on the first buffer layer. A first channel region is disposed between the first trench and the second trench and disposed in the substrate. A first gate electrode is disposed on the first channel area. A third trench is disposed in the PMOS region. A second buffer layer is disposed in the third trench. A second channel area is disposed in the third trench, disposed on the second buffer layer, and has a different semiconductor layer from the substrate. A second gate electrode is disposed on the second channel area.

Abstract translation: 如下提供半导体器件。 衬底包括NMOS区和PMOS区。 第一沟槽和第二沟槽设置在NMOS区域中。 第一缓冲层设置在第一沟槽和第二沟槽中。 应力器设置在第一沟槽和第二沟槽中并且设置在第一缓冲层上。 第一沟道区域设置在第一沟槽和第二沟槽之间并且设置在衬底中。 第一栅电极设置在第一沟道区上。 第三沟槽设置在PMOS区域中。 第二缓冲层设置在第三沟槽中。 第二沟道区域设置在第三沟槽中，设置在第二缓冲层上，并且与衬底具有不同的半导体层。 第二栅电极设置在第二沟道区上。