公开(公告)号：US4937756A

公开(公告)日：1990-06-26

申请号：US300582

申请日：1989-01-23

申请人： Je-Jung Hsu ,  Hsing-Hai Chen

发明人： Je-Jung Hsu ,  Hsing-Hai Chen

IPC分类号： H01L21/765

CPC分类号： H01L21/765 ,  Y10S257/906 ,  Y10S438/953

摘要： The invention relates to a radiation-hardened (R-H) bulk CMOS process which is compatible with DRAM production and a specific gated isolation structure (GIS). The GIS structure consists of a novel oxide-silicon nitride-oxynitride gate insulator and a LPCVD polysilicon gate. A simple but automatically generating process for creating GIS directly from an original non-R-H device is also described. This generating process is fast and can revise any commercial products to a R-H version. The GIS is always shunted to Vss potential of the circuit chip to assure R-H capability. The grounded GIS structure replaces conventional LOCOS field oxide, which suffers from large threshold voltage shift when exposed to irradiation. Radiation resistance of this gated isolation structure (GIS) is suitable for application in radiation-immunity VLSI integrated circuits (.ltoreq.2um design rule).

摘要翻译： 本发明涉及与DRAM生产和特定的门控隔离结构（GIS）兼容的辐射硬化（R-H）体CMOS工艺。 GIS结构由新型氧化物 - 氮化硅 - 氮氧化物栅极绝缘体和LPCVD多晶硅栅极组成。 还描述了一种用于从原始非R-H设备直接创建GIS的简单但自动生成的过程。 这个生成过程很快，可以将任何商业产品修改为R-H版本。 GIS总是分流到电路芯片的Vss电位，以确保R-H能力。 接地的GIS结构代替常规的LOCOS场氧化物，当暴露于照射时，其具有大的阈值电压偏移。 该门控隔离结构（GIS）的抗辐射性适用于放射免疫VLSI集成电路（

公开(公告)号：US4849366A

公开(公告)日：1989-07-18

申请号：US144272

申请日：1988-01-15

申请人： Je-Jung Hsu ,  Hsing-Hai Chen

发明人： Je-Jung Hsu ,  Hsing-Hai Chen

IPC分类号： H01L29/78 ,  H01L21/76 ,  H01L21/765 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/765 ,  Y10S438/953

摘要： The invention relates to a radiation hardened (R-H) bulk complementary metal oxide semiconductor (CMOS) isolation structure and a process for its formation. The isolation structure may be automatically generated from the original thin oxide layer of any commercial product by computer aided design and basically comprises a grounded MOS gate surrounding the active areas. The grounded MOS gate replaces the conventional LOCOS field oxide and consists of novel oxide-silicon nitride-oxynitride gate insulator and a CVD polysilicon film. The radiation resistance of this gated isolated structure (GIS) is suitable for application in radiation-immunity VLSI integrated circuit (.ltoreq.2 .mu.m design rule).

公开(公告)号：US5877060A

公开(公告)日：1999-03-02

申请号：US837462

申请日：1997-04-18

申请人： Je-Jung Hsu

发明人： Je-Jung Hsu

IPC分类号： H01L21/768 ,  H01L21/8244 ,  H01L27/11 ,  H01L21/20

CPC分类号： H01L27/11 ,  H01L21/76889 ,  H01L27/1112

摘要： A method for fabricating SRAM polyloads that allows device dimension reduction yet maintains overall product functionality which includes the following steps: forming an insulating layer above a semiconductor substrate having a conductive gate device and a conductive voltage source line device already formed in it; etching the insulating layer selectively, and forming a first contact window and a second contact window on the surfaces of the conductive gate device and the conductive voltage source line device respectively; forming a polysilicon layer above the insulating layer, and filling up the first and the second contact windows at the same time; forming a silicide layer above the polysilicon layer; etching the silicide layer and the polysilicon layer to form a conductive wire linking the first contact window with the second contact window; and etching selectively section of the silicide layer on the conductive wire to expose the polysilicon layer below, and forming a polyload in the exposed polysilicon layer region thus created.

摘要翻译： 一种用于制造SRAM多重负载的方法，其允许器件尺寸减小但保持整体产品功能性，其包括以下步骤：在已经形成有导电栅极器件和导电电压源线器件的半导体衬底上形成绝缘层; 选择性地蚀刻绝缘层，并分别在导电栅极器件和导电电压源线器件的表面上形成第一接触窗口和第二接触窗口; 在绝缘层上方形成多晶硅层，同时填充第一和第二接触窗口; 在所述多晶硅层上形成硅化物层; 蚀刻硅化物层和多晶硅层以形成将第一接触窗与第二接触窗连接的导线; 并且蚀刻导电线上的硅化物层的选择性部分以暴露下面的多晶硅层，并在由此产生的暴露的多晶硅层区域中形成多重负载。