公开(公告)号：US10931369B2

公开(公告)日：2021-02-23

申请号：US16829360

申请日：2020-03-25

Applicant: Juniper Networks, Inc.

Inventor： Remo Maccaglia ,  Gert Grammel

IPC: H04B10/079 ,  H04L1/00 ,  H04L1/20 ,  H04J14/02 ,  H04L12/707 ,  H04L12/24 ,  H04L12/26 ,  G06N20/00 ,  H04L12/703 ,  H04B10/038

Abstract: In some embodiments, an apparatus comprises a memory and a processor operatively coupled to the memory. The processor is configured to receive, from a forward error correction (FEC) decoder of an optical transponder, a first plurality of pre-FEC bit error rate (BER) values at a plurality of times to identify a degradation over a first transmission path. The processor is configured to determine, based on the first plurality of pre-FEC BER values, a signal pattern. The processor is configured to adjust, based on the signal pattern, a set of parameters including a first threshold and a second threshold. The processor is configured to send, in response to a second pre-FEC BER value exceeding the second threshold and being below the first threshold, a signal to trigger traffic rerouting to a second transmission path to reduce traffic loss due to the degradation over the first transmission path.