公开(公告)号：US11379187B2

公开(公告)日：2022-07-05

申请号：US16834706

申请日：2020-03-30

Applicant: SK hynix Inc. ,  Korea Advanced Institute of Science and Technology (KAIST)

Inventor： Jin-O Seo ,  Hyuk-Jin Lee ,  SeongHwan Cho

IPC: G06F7/544 ,  G06F7/523 ,  G11C11/4096 ,  G06N3/04

Abstract: A semiconductor device includes a cell array, a computation circuit, and a control circuit. The cell array includes a plurality of unit cells configured to store a plurality of first signals by a write operation and to output a plurality of output signals corresponding to the first signals by a read operation. The computation circuit includes a plurality of unit computation circuits receiving the plurality of output signals and being set according to a plurality of second signals during a computation operation. The control circuit is configured to control the cell array and the computation circuit during the write operation, the read operation, and the computation operation.

公开(公告)号：US11526739B2

公开(公告)日：2022-12-13

申请号：US16838916

申请日：2020-04-02

Applicant: SK hynix Inc. ,  Korea Advanced Institute of Science and Technology (KAIST)

Inventor： Jin-O Seo ,  Hyuk-Jin Lee ,  SeongHwan Cho

IPC: G11C7/00 ,  G06N3/063 ,  G11C16/04 ,  G06N3/04 ,  G11C16/08 ,  G06F7/523 ,  G11C16/24

Abstract: A nonvolatile memory device includes a memory cell array and an computation output circuit. The memory cell array includes a plurality of nonvolatile memory elements configured to store a plurality of weights respectively and a plurality of bit lines coupled to the plurality of nonvolatile memory elements according to a plurality of input signals. The computation output circuit is configured to generate a computation signal from voltages induced at the plurality of bit lines according to the plurality of input signals.

公开(公告)号：US11803354B2

公开(公告)日：2023-10-31

申请号：US17178592

申请日：2021-02-18

Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Seonghwan Cho ,  Hyuk Jin Lee ,  Kyung Hyun Kim ,  Jin-O Seo

IPC: G06F7/544 ,  G06G7/16

CPC classification number: G06F7/5443 ,  G06G7/16 ,  G06F2207/4814

Abstract: A MAC operating device comprising a plurality of operation circuits respectively including an operation capacitor and a plurality of switches; and a division capacitor, wherein one end of the operation capacitor is respectively connected to a first operation switch connected to an input terminal and a first reset switch connected to a ground terminal, and the other end of the operation capacitor is connected to both a second operation switch connected to a division capacitor and a second reset switch connected to the ground terminal is provided.

公开(公告)号：US20220206756A1

公开(公告)日：2022-06-30

申请号：US17178592

申请日：2021-02-18

Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Seonghwan Cho ,  Hyuk Jin Lee ,  Kyung Hyun Kim ,  Jin-O Seo

IPC: G06F7/544 ,  G06F7/52 ,  G06F9/30 ,  G11C7/10

Abstract: A MAC operating device comprising a plurality of operation circuits respectively including an operation capacitor and a plurality of switches; and a division capacitor, wherein one end of the operation capacitor is respectively connected to a first operation switch connected to an input terminal and a first reset switch connected to a ground terminal, and the other end of the operation capacitor is connected to both a second operation switch connected to a division capacitor and a second reset switch connected to the ground terminal is provided.