公开(公告)号：US12164981B2

公开(公告)日：2024-12-10

申请号：US17198448

申请日：2021-03-11

Applicant: Kioxia Corporation

Inventor： Radu Berdan ,  Daisuke Miyashita ,  Jun Deguchi

IPC: G06G7/16 ,  G06F7/544

Abstract: According to one embodiment, in a processing circuit of a computation system, a plurality of comparators corresponds to the respective columns, each including a first input node, a second input node, and an output node, the first input node receiving any one of the second signals, the second input node receiving a signal corresponding to a global reference signal provided to each second input node, the output node outputting a local signal. A global circuit is provided common to the plurality of comparators, the global circuit generating a global signal according to a plurality of the local signals, the global circuit generating the global reference signal by an SAR method according to the global signal. The processing circuit disables some of the plurality of comparators according to the local signals and the global signal.