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    Methods of forming CMOS integrated circuits that utilize insulating layers with high stress characteristics to improve NMOS and PMOS transistor carrier mobilities
    1.
    发明授权
    Methods of forming CMOS integrated circuits that utilize insulating layers with high stress characteristics to improve NMOS and PMOS transistor carrier mobilities 有权
    使用具有高应力特性的绝缘层的CMOS集成电路的方法来改善NMOS和PMOS晶体管载流子迁移率

    公开(公告)号：US07781276B2

    公开(公告)日：2010-08-24

    申请号：US12353519

    申请日：2009-01-14

    申请人： Kyoung-woo Lee ,  Ja-hum Ku ,  Seung-man Choi

    发明人： Kyoung-woo Lee ,  Ja-hum Ku ,  Seung-man Choi

    IPC分类号： H01L21/337

    CPC分类号： H01L21/823807 ,  H01L29/7843

    摘要： A CMOS integrated circuit has NMOS and PMOS transistors therein and an insulating layer extending on the NMOS transistors. The insulating layer is provided to impart a relatively large tensile stress to the NMOS transistors. In particular, the insulating layer is formed to have a sufficiently high internal stress characteristic that imparts a tensile stress in a range from about 2 gigapascals (2 GPa) to about 4 gigapascals (4 GPa) in the channel regions of the NMOS transistors.

    摘要翻译： CMOS集成电路在其中具有NMOS和PMOS晶体管，并且在NMOS晶体管上延伸绝缘层。 提供绝缘层以向NMOS晶体管施加相对较大的拉伸应力。 特别地，绝缘层被形成为具有足够高的内部应力特性，其在NMOS晶体管的沟道区域中赋予约2千兆帕（2GPa）至约4千兆帕（4GPa）的范围内的拉伸应力。

    Methods of Forming CMOS Integrated Circuits that Utilize Insulating Layers with High Stress Characteristics to Improve NMOS and PMOS Transistor Carrier Mobilities
    2.
    发明申请
    Methods of Forming CMOS Integrated Circuits that Utilize Insulating Layers with High Stress Characteristics to Improve NMOS and PMOS Transistor Carrier Mobilities 有权
    使用具有高应力特性的绝缘层的CMOS集成电路的形成方法来改善NMOS和PMOS晶体管载体的迁移率

    公开(公告)号：US20090124093A1

    公开(公告)日：2009-05-14

    申请号：US12353519

    申请日：2009-01-14

    申请人： Kyoung-woo Lee ,  Ja-hum Ku ,  Seung-man Choi

    发明人： Kyoung-woo Lee ,  Ja-hum Ku ,  Seung-man Choi

    IPC分类号： H01L21/469

    CPC分类号： H01L21/823807 ,  H01L29/7843

    摘要： A CMOS integrated circuit has NMOS and PMOS transistors therein and an insulating layer extending on the NMOS transistors. The insulating layer is provided to impart a relatively large tensile stress to the NMOS transistors. In particular, the insulating layer is formed to have a sufficiently high internal stress characteristic that imparts a tensile stress in a range from about 2 gigapascals (2 GPa) to about 4 gigapascals (4 GPa) in the channel regions of the NMOS transistors.

    摘要翻译： CMOS集成电路在其中具有NMOS和PMOS晶体管，并且在NMOS晶体管上延伸绝缘层。 提供绝缘层以向NMOS晶体管施加相对较大的拉伸应力。 特别地，绝缘层被形成为具有足够高的内部应力特性，其在NMOS晶体管的沟道区域中赋予约2千兆帕（2GPa）至约4千兆帕（4GPa）的范围内的拉伸应力。

    Method of forming a metal interconnection of a semiconductor device, and metal interconnection formed by such method
    4.
    发明申请
    Method of forming a metal interconnection of a semiconductor device, and metal interconnection formed by such method 有权
    形成半导体器件的金属互连的方法以及通过这种方法形成的金属互连

    公开(公告)号：US20060177630A1

    公开(公告)日：2006-08-10

    申请号：US11336905

    申请日：2006-01-23

    申请人： Sun-jung Lee ,  Soo-geun Lee ,  Hong-jae Shin ,  Andrew-tae Kim ,  Seung-man Choi ,  Bong-seok Suh

    发明人： Sun-jung Lee ,  Soo-geun Lee ,  Hong-jae Shin ,  Andrew-tae Kim ,  Seung-man Choi ,  Bong-seok Suh

    IPC分类号： B32B3/04

    CPC分类号： H01L21/76877 ,  H01L21/7684 ,  H01L21/76883 ,  Y10T428/24207

    摘要： A metal interconnection of a semiconductor device, formed using a damascene process, has large grains and yet a smooth surface. First, a barrier layer and a metal layer are sequentially formed in an opening in an interlayer dielectric layer. A CMP process is carried out on the metal layer to form a metal interconnection remaining within the opening. Then, the metal interconnection is treated with plasma. The plasma treatment creates compressive stress in the metal interconnection, which stress produces hillocks at the surface of the metal interconnection. In addition, the plasma treatment process causes grains of the metal to grow, especially when the design rule is small, to thereby decrease the resistivity of the metal interconnection. The hillocks are then removed by a CMP process aimed at polishing the portion of the barrier layer that extends over the upper surface of the interlayer dielectric layer. Finally, a capping insulating layer is formed. The intentional forming of hillocks by the plasma treatment process at weak portions of the metal interconnection and the subsequent removal of the hillocks greatly reduces the possibility of any additional hillocks being produced at the surface of the metal interconnection, especially when the capping layer is formed.

    摘要翻译： 使用镶嵌工艺形成的半导体器件的金属互连具有大的晶粒并且具有光滑的表面。 首先，在层间电介质层的开口中依次形成阻挡层和金属层。 在金属层上进行CMP工艺以形成残留在开口内的金属互连。 然后，用等离子体处理金属互连。 等离子体处理在金属互连中产生压应力，该应力在金属互连表面产生小丘。 此外，等离子体处理工艺使得金属晶粒生长，特别是当设计规则小时，从而降低金属互连的电阻率。 然后通过CMP工艺去除小丘，目的是抛光在层间电介质层的上表面上延伸的阻挡层的部分。 最后，形成封盖绝缘层。 通过等离子体处理在金属互连的弱部分和随后的小丘的移除中有意形成小丘大大减少了在金属互连表面产生任何额外的小丘的可能性，特别是当形成覆盖层时。

    Method of forming a metal interconnection of a semiconductor device, and metal interconnection formed by such method
    8.
    发明授权
    Method of forming a metal interconnection of a semiconductor device, and metal interconnection formed by such method 有权
    形成半导体器件的金属互连的方法以及通过这种方法形成的金属互连

    公开(公告)号：US07446033B2

    公开(公告)日：2008-11-04

    申请号：US11336905

    申请日：2006-01-23

    申请人： Sun-jung Lee ,  Soo-geun Lee ,  Hong-jae Shin ,  Andrew-tae Kim ,  Seung-man Choi ,  Bong-seok Suh

    发明人： Sun-jung Lee ,  Soo-geun Lee ,  Hong-jae Shin ,  Andrew-tae Kim ,  Seung-man Choi ,  Bong-seok Suh

    IPC分类号： H01L21/4763 ,  H01L21/44

    CPC分类号： H01L21/76877 ,  H01L21/7684 ,  H01L21/76883 ,  Y10T428/24207

    摘要： A metal interconnection of a semiconductor device, formed using a damascene process, has large grains and yet a smooth surface. First, a barrier layer and a metal layer are sequentially formed in an opening in an interlayer dielectric layer. A CMP process is carried out on the metal layer to form a metal interconnection remaining within the opening. Then, the metal interconnection is treated with plasma. The plasma treatment creates compressive stress in the metal interconnection, which stress produces hillocks at the surface of the metal interconnection. In addition, the plasma treatment process causes grains of the metal to grow, especially when the design rule is small, to thereby decrease the resistivity of the metal interconnection. The hillocks are then removed by a CMP process aimed at polishing the portion of the barrier layer that extends over the upper surface of the interlayer dielectric layer. Finally, a capping insulating layer is formed. The intentional forming of hillocks by the plasma treatment process at weak portions of the metal interconnection and the subsequent removal of the hillocks greatly reduces the possibility of any additional hillocks being produced at the surface of the metal interconnection, especially when the capping layer is formed.

    摘要翻译： 使用镶嵌工艺形成的半导体器件的金属互连具有大的晶粒并且具有光滑的表面。 首先，在层间电介质层的开口中依次形成阻挡层和金属层。 在金属层上进行CMP工艺以形成残留在开口内的金属互连。 然后，用等离子体处理金属互连。 等离子体处理在金属互连中产生压应力，该应力在金属互连表面产生小丘。 此外，等离子体处理工艺使得金属晶粒生长，特别是当设计规则小时，从而降低金属互连的电阻率。 然后通过CMP工艺去除小丘，目的是抛光在层间电介质层的上表面上延伸的阻挡层的部分。 最后，形成封盖绝缘层。 通过等离子体处理在金属互连的弱部分和随后的小丘的移除中有意形成小丘大大减少了在金属互连表面产生任何额外的小丘的可能性，特别是当形成覆盖层时。