Abstract:
Disclosed are a shift register and a flat panel display device. The shift register includes a plurality of stages that supply a gate-on voltage pulse to a plurality of gate lines formed in a display panel. Each of the stages includes a pull-up transistor configured to supply one of a plurality of clock signals to an output node according to a voltage of a first node, a pull-down transistor configured to supply a gate-off voltage to the output node according to a voltage of a second node, a node controller configured to control the voltages of the first and second nodes on the basis of a gate start signal, and a switching unit connected to at least two gate lines adjacent to the output node, and configured to sequentially supply gate-on voltage pulses having different pulse widths to the at least two adjacent gate lines using the clock signal.
Abstract:
A display device according to one or more examples may include a substrate, a display area with a first display area and a second display area, a non-display area, a base circuit layer located on the substrate and including a gate-in-panel circuit and a subpixel circuit array disposed in the display area, and a light emitting device layer located on the base circuit layer and including two or more first light emitting devices disposed in the first display area and two or more second light emitting devices disposed in the second display area. The subpixel circuit array may include one first subpixel circuit configured to simultaneously drive the two or more first light emitting devices, and disposed in the second display area, and two or more second subpixel circuits configured to respectively drive the two or more second light emitting devices, and disposed in the second display area.
Abstract:
A display device according to one or more examples may include a substrate, a pixel array layer located on the substrate and including a plurality of subpixels disposed in a display area where an image is displayed, and a base circuit layer located between the substrate and the pixel array layer and including a gate driving circuit disposed over the entire display area. A display panel and a display apparatus are also disclosed.
Abstract:
A display device can include a plurality of sub pixels disposed on a substrate; a first driver disposed in each of the plurality of sub pixels, the first driver being configured to generate a first driving current for a normal mode in which an image is displayed in a luminance range equal to or lower than a predetermined luminance; a second driver disposed in each of the plurality of sub pixels, the second driver being configured to generate a second driving current for a high luminance mode in which the luminance range is higher than the predetermined luminance; and a light emitting diode. Also, the light emitting diode is configured to receive the first driving current in the normal mode, and receive a sum of the first driving current and the second driving current in the high luminance mode.