公开(公告)号：US11658685B2

公开(公告)日：2023-05-23

申请号：US17494361

申请日：2021-10-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chin-Chu Chung ,  Chien-Hsin Liu ,  Hung-Jen Kao ,  Yu-Chih Yeh

IPC: H03M13/00 ,  H03M13/35 ,  G06F11/10

CPC classification number: H03M13/356 ,  G06F11/1068

Abstract: A storage device includes a memory array and a memory controller. The memory controller generates read and write commands for the memory array. An error correction code engine for the storage device is operable to use a plurality of different codeword sizes, different code rates, or different ECC algorithms. Logic is included that applies a selected codeword size, code rate or ECC algorithm in dependence on the operating conditions of the memory array.

公开(公告)号：US20220342597A1

公开(公告)日：2022-10-27

申请号：US17238757

申请日：2021-04-23

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chien-Hsin Liu ,  Yu-Chih Yeh ,  Chin-Chu Chung

IPC: G06F3/06

Abstract: A memory comprising a memory array, including a plurality of blocks, and control circuits comprising logic to execute operations is provided. The operations include decoding a read setup burst command identifying (i) an address of a first read setup block in a set of read setup blocks and (ii) a number of read setup blocks, as candidates for read setup operations. The operations further including, in response to the decoding of the read setup burst command, performing a read setup burst operation on a plurality of read setup blocks of the set of read setup blocks.

公开(公告)号：US11385839B1

公开(公告)日：2022-07-12

申请号：US17242123

申请日：2021-04-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chin-Chu Chung ,  Chien-Hsin Liu ,  Yu-Chih Yeh

IPC: G06F3/06

Abstract: A method of operating a memory is provided. The method includes, in response to an access of a block of memory updating a first queue to identify the accessed block in response to a determination that the block is not already identified in the first queue and a determination that the block is not already identified in a second queue, and updating the second queue to identify the accessed block of memory in response to a determination that the block is already identified in the first queue. The method further includes scanning the second queue to identify, as a read setup candidate, each block of the memory that is identified as present in the second queue longer than a threshold, and performing a read setup operation on a block of memory that has been identified as the read setup candidate.

公开(公告)号：US11803326B2

公开(公告)日：2023-10-31

申请号：US17238757

申请日：2021-04-23

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chien-Hsin Liu ,  Yu-Chih Yeh ,  Chin-Chu Chung

IPC: G06F3/00 ,  G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0688

Abstract: A memory comprising a memory array, including a plurality of blocks, and control circuits comprising logic to execute operations is provided. The operations include decoding a read setup burst command identifying (i) an address of a first read setup block in a set of read setup blocks and (ii) a number of read setup blocks, as candidates for read setup operations. The operations further including, in response to the decoding of the read setup burst command, performing a read setup burst operation on a plurality of read setup blocks of the set of read setup blocks.