公开(公告)号：US20250117137A1

公开(公告)日：2025-04-10

申请号：US18905398

申请日：2024-10-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jay Sarkar ,  David Scott Ebsen ,  Aaron Lucas ,  Seyhan Karakulak ,  Saeed Sharifi Tehrani

IPC: G06F3/06

Abstract: Systems and methods are disclosed including a memory and a processing device operatively coupled to the memory. The processing device can perform operations including identifying a set of logical addresses associated with data stored on the memory devices in one or more blocks of a first type; determining a temporal metric class associated with the set of logical addresses, wherein the temporal metric class is associated with a corresponding range of predicted update characteristic of the data; identifying, based on the temporal metric class, a set of blocks of a second type, wherein a first block of the first type comprises a first plurality of memory cells having a first number of bits per cell, and wherein a second block of the second type comprises a second plurality of memory cells having a second number of bits per cell that exceeds the first number of bits per cell; and moving the data to the identified set of blocks.