公开(公告)号：US20240220259A1

公开(公告)日：2024-07-04

申请号：US18525083

申请日：2023-11-30

Applicant: Meta Platforms Technologies, LLC

Inventor： Tomonari Tohara ,  Vignesh Vivekraja ,  Alagappan Valliappan ,  Andrey Bushev ,  Javid Jaffari

IPC: G06F9/30

CPC classification number: G06F9/30178 ,  G06F9/30038 ,  G06F9/30134

Abstract: In one embodiment, a computing system may set data to a first group of registers. The first group of registers may be configured to be accessed during a single operation cycle. The system may set a number of patterns to a second group of registers. Each pattern of the number of patterns may include an array of index for the data stored in the first group of registers. The system may select, for a first vector register associated with a vector engine, a first pattern from the patterns stored in the second group of registers. The system may load a first portion of the data from the first group of registers to the first vector register based on the first pattern selected for the first vector register from the patterns stored in the second group of registers.