利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

121 条记录 (耗时 0.027 秒)

    Automating photolithography in the fabrication of integrated circuits
    1.
    再颁专利
    Automating photolithography in the fabrication of integrated circuits 有权
    在制造集成电路时自动化光刻

    公开(公告)号：USRE38900E1

    公开(公告)日：2005-11-29

    申请号：US09273171

    申请日：1999-03-19

    申请人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Ashok K. Kapoor

    发明人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Ashok K. Kapoor

    IPC分类号： G03F7/20 ,  H01L21/66

    CPC分类号： G03F7/705 ,  G03F7/20 ,  G03F7/70433

    摘要： Automated photolithography of integrated circuit wafers is enabled with a processor connected to a Rayleigh derator, a form factor generator, a logic synthesizer, a layout generator, a lithography module and a wafer process. The Rayleigh derator receives manufacturing information resulting from yield data in the wafer process, and this manufacturing data is then used to derate the theoretical minimum feature size available for etching wafer masks given a known light source and object lens numerical aperture. This minimum feature size is then used by a form factor generator in sizing transistors in a net list to their smallest manufacturable size. A logic synthesizer then converts the net list into a physical design using a layout generator combined with user defined constraints. This physical design is then used by the mask lithography module to generate wafer masks for use in the semiconductor manufacturing. Manufacturing data including process and yield parameters is then transferred back to the Rayleigh processor for use in the designing of subsequent circuits. In this way, a direct coupling exists between the measurement of wafer process parameters and the automated sizing of semiconductor devices, enabling the production of circuits having the smallest manufacturable device sizes available for the given lithography and wafer process.

    摘要翻译： 集成电路晶片的自动光刻可通过连接到瑞利分离器，形状因子发生器，逻辑合成器，布局发生器，光刻模块和晶片工艺的处理器来实现。 Rayleigh变矩器接收由晶片工艺中的屈服数据产生的制造信息，然后使用该制造数据降低可用于蚀刻具有已知光源和物镜数值孔径的晶片掩模的理论最小特征尺寸。 然后，这种最小特征尺寸由形状因子发生器用于将网络列表中的晶体管调整到其最小可制造尺寸。 然后，逻辑合成器将网络列表转换为使用布局生成器与用户定义的约束组合的物理设计。 然后该掩模光刻模块将该物理设计用于半导体制造中使用的晶片掩模。 然后将包括处理和产量参数的制造数据传送回瑞利处理器，以用于后续电路的设计。 以这种方式，在晶片工艺参数的测量和半导体器件的自动化尺寸之间存在直接耦合，使得能够生产具有可用于给定光刻和晶片工艺的最小可制造器件尺寸的电路。

    Process for performing low wavelength photolithography on semiconductor wafer using afocal concentration
    2.
    发明授权
    Process for performing low wavelength photolithography on semiconductor wafer using afocal concentration 失效
    使用无焦点浓度在半导体晶片上进行低波长光刻的工艺

    公开(公告)号：US5666189A

    公开(公告)日：1997-09-09

    申请号：US519797

    申请日：1995-08-28

    申请人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Joe Zelayeta

    发明人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Joe Zelayeta

    IPC分类号： G03F7/20 ,  G03B27/42

    CPC分类号： G03F7/70008 ,  G03F7/702 ,  G03F7/70375 ,  Y10S430/167

    摘要： Fine, sub-micron line features and patterns are created in a sensitized layer on a semiconductor wafer by a beam of low wavelength radiation, such as X-rays or Gamma-rays. A stream of such radiation is concentrated and collimated by a concentrator, the output of which is disposed in close proximity to the sensitized surface of the wafer. In this manner, the sensitized surface can be converted from one chemical state to another chemical state, essentially point-by-point. By moving one or the other of the beam or the wafer, line features can be converted in the sensitized surface. Typically, non-converted areas of the sensitized surface are removed, for further processing a layer underlying the sensitized surface. The concentrator is useful in for directing a stream of radiation from a continuously emitting source, such as from a pellet of Cobalt-60, onto the sensitized surface of the wafer when a shutter mechanism is incorporated either upstream (towards the source) or downstream (towards the wafer) from the concentrator.

    摘要翻译： 通过诸如X射线或γ射线的低波长辐射束在半导体晶片上的增感层中产生细微亚微米线特征和图案。 这种辐射流被集中器集中并准直，该集中器的输出设置在晶片敏感表面附近。 以这种方式，致敏表面可以从一个化学状态转变为另一个化学状态，基本上是逐点的。 通过移动光束或晶片中的一个或另一个，可以在致敏表面中转换线特征。 通常，去除敏化表面的未转化区域，以进一步处理敏化表面下面的层。 浓缩器可用于在将快门机构并入上游（朝向源）或下游（在源头）处引入来自连续发射源的辐射流，例如由钴-60颗粒沉积到晶片的致敏表面上（ 朝向晶片）。

    Depositing and densifying glass to planarize layers in semi-conductor devices based on CMOS structures
    4.
    发明授权
    Depositing and densifying glass to planarize layers in semi-conductor devices based on CMOS structures 失效
    沉积和致密化玻璃以基于CMOS结构在半导体器件中平坦化层

    公开(公告)号：US5514616A

    公开(公告)日：1996-05-07

    申请号：US278573

    申请日：1994-07-21

    申请人： Michael D. Rostoker ,  Nicholas F. Pasch

    发明人： Michael D. Rostoker ,  Nicholas F. Pasch

    IPC分类号： H01L21/266 ,  H01L21/3105 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/316

    CPC分类号： H01L21/31051 ,  H01L21/266 ,  H01L21/3105 ,  H01L21/31053 ,  H01L21/823871 ,  Y10S438/981

    摘要： Methods of planarizing one or more layers having an irregular top surface topology in a semiconductor device based on an underlying MOS structure are disclosed. Methods of creating doped wells or regions for the underlying MOS structure are also disclosed, using thick oxide growths on the surface of the substrate to mask implantation of ions into the wells. A technique for creating a pair of adjacent complementary oppositely-doped wells, such as for a CMOS structure, using a thick oxide growths as a mask is also disclosed. One of the methods of planarizing the one or more layers involves depositing, densifying and re-flowing a layer of glass on top of the topological layer. Another method of planarizing the one or more layers involves depositing, densifying and chemical-mechanically polishing the deposited and densified glass, thereby avoiding an additional temperature cycle (i.e., for re-flowing the glass) which would adversely affect underlying diffusions.

    摘要翻译： 公开了基于下面的MOS结构在半导体器件中平面化具有不规则顶表面拓扑的一个或多个层的方法。 还公开了为底层MOS结构产生掺杂阱或区域的方法，其使用在衬底表面上的厚氧化物生长来掩蔽将离子注入到阱中。 还公开了一种用于产生一对相邻的互补相对掺杂阱的技术，例如使用厚氧化物生长作为掩模的CMOS结构。 对一个或多个层进行平坦化的方法之一包括在拓扑层顶部沉积，致密化和再流动玻璃层。 平面化一个或多个层的另一种方法包括沉积，致密化和化学机械抛光沉积的和致密化的玻璃，从而避免对底层扩散产生不利影响的附加温度循环（即，用于重新流动玻璃）。

    Image masks for semiconductor lithography
    5.
    发明授权
    Image masks for semiconductor lithography 失效
    用于半导体光刻的图像掩模

    公开(公告)号：US5512395A

    公开(公告)日：1996-04-30

    申请号：US340251

    申请日：1994-11-16

    申请人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Joe Zelayeta

    发明人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Joe Zelayeta

    IPC分类号： G03F1/22 ,  G03F7/20 ,  G03F9/00

    CPC分类号： G03F1/22 ,  G03F7/2039

    摘要： Fine, sub-micron line features and patterns are created in a sensitized layer on a semiconductor wafer by a beam of low wavelength radiation, such as X-rays. The X-ray source emits very low wavelength radiation along a path towards a sensitized surface of a semiconductor wafer. An image mask substrate is disposed in the path of the radiation, and is provided with opaque material on a surface thereof, forming a pattern. The image mask is spaced sufficiently close to the wafer that radiation passing through the mask forms a corresponding pattern in the surface of the wafer. For X-ray radiation, the opaqueing material is gold, tungsten, platinum, barium, lead, iridium, rhodium, or the like.

    摘要翻译： 通过诸如X射线的低波长辐射束在半导体晶片上的增感层中产生细的亚微米线特征和图案。 X射线源沿着朝向半导体晶片的敏化表面的路径发射非常低的波长辐射。 图像掩模基板设置在辐射的路径中，并且在其表面上设置有不透明材料，形成图案。 图像掩模与晶片充分地间隔开，通过掩模的辐射在晶片表面形成相应的图案。 对于X射线辐射，不透明材料是金，钨，铂，钡，铅，铱，铑等。

    Integrated circuit having interconnects with ringing suppressing elements
    6.
    发明授权
    Integrated circuit having interconnects with ringing suppressing elements 失效
    具有与振铃抑制元件互连的集成电路

    公开(公告)号：US5442225A

    公开(公告)日：1995-08-15

    申请号：US106175

    申请日：1993-08-13

    申请人： Michael D. Rostoker ,  Nicholas F. Pasch

    发明人： Michael D. Rostoker ,  Nicholas F. Pasch

    IPC分类号： H01L23/522 ,  H01L27/02

    CPC分类号： H01L23/5222 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/3011

    摘要： Apparatus for improving ON/OFF switching in high speed digital circuitry is disclosed. The present invention includes apparatus for altering the impedance or capacitive loading of the interconnect. Some embodiments reduce back reflections by raising the impedance of the interconnect to be closer to that of the contact, or raising the capacitive loading, and others improve the culprit-victim problem by filtering out the highest frequency components of the pulse on the culprit interconnect. For the back reflection problem, the apparatus for altering can be formed of elements for altering the capacitance or, alternatively the resistance, of the interconnect. For the culprit-victim problem, the apparatus for altering includes elements which alter the effective capacitance or resistance of the culprit interconnect.

    摘要翻译： 公开了一种用于改善高速数字电路中的ON / OFF切换的装置。 本发明包括用于改变互连的阻抗或电容负载的装置。 一些实施例通过将互连的阻抗提高到更接近触点的阻抗或提高电容负载来减少反射反射，并且其他实施例通过滤除歹徒互连上的脉冲的最高频率分量来改善凶手 - 受害者问题。 对于背反射问题，用于改变的装置可以由用于改变互连的电容或替代地阻抗的元件形成。 对于罪魁祸首的问题，变更装置包括改变歹徒互连的有效电容或电阻的元件。

    Off-axis power branches for interior bond pad arrangements
    7.
    发明授权
    Off-axis power branches for interior bond pad arrangements 失效
    离轴电源分支用于内部接合焊盘布置

    公开(公告)号：US5384487A

    公开(公告)日：1995-01-24

    申请号：US58120

    申请日：1993-05-05

    申请人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Joe Zelayeta

    发明人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Joe Zelayeta

    IPC分类号： H01L23/485 ,  H01L23/50 ,  H01L23/48 ,  H01L29/44 ,  H01L29/52 ,  H01L29/60

    CPC分类号： H01L24/06 ,  H01L23/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/351

    摘要： A technique for improving power distribution to an semiconductor die while simultaneously reducing thermally-induced mechanical stresses on bond pads in semiconductor device assemblies is accomplished by providing the signal-carrying bond pads in a collinear arrangement along an axis of the die, and providing power-carrying bond pads in an off-axis location. The on-axis configuration of signal-carrying bond pads minimizes lateral thermal displacements of the bond pads relative to the axis, which minimizes any longitudinal, compressive end displacements of leadframe fingers or bond wires, thereby minimizing thermally induced mechanical stresses of the bond pad interfaces to the die. The positioning of the power-carrying bond pads off-axis reduces the length of internal (to the die) wiring required to connect circuitry on the die to the power-carrying bond pads. Constraining the location of the power-carrying bond pads to an interior area of the die approximately one half of the die area, and substantially centered about the axis, keeps longitudinal thermal displacements of the ends of leadframe fingers or bond wires connected to the power-carrying bond pads relatively small compared to those experienced in peripheral bond pad placement (at the die edges), and ensures shorter, more direct internal paths to circuitry on the die.

    摘要翻译： 一种用于改善对半导体管芯的功率分配的同时降低半导体器件组件中的接合焊盘上的热诱导机械应力的技术是通过沿着管芯的轴线以共线布置提供信号承载接合焊盘来实现的， 在离轴位置承载接合焊盘。 信号承载接合焊盘的轴上构造使接合焊盘相对于轴的横向热位移最小化，这使引线框架指或接合线的任何纵向，压缩端移动最小化，从而最小化接合焊盘界面的热致机械应力 去死 功率承载接合垫离轴的定位减少了将管芯上的电路连接到功率承载接合焊盘所需的内部（针对芯片）布线的长度。 将功率承载接合焊盘的位置限制在模具的内部区域中大约是模具区域的一半，并且基本上围绕轴线居中，保持引线框架指状物的端部或连接到电源接合焊盘的接合线的纵向热位移， 与在外围接合焊盘放置（在模具边缘）处经历的相比，承载焊盘相对较小，并确保对芯片上的电路的更短，更直接的内部路径。

    Identifying and compensating for slip-plane dislocations in photolithographic mask alignment
    8.
    发明授权
    Identifying and compensating for slip-plane dislocations in photolithographic mask alignment 失效
    识别和补偿光刻掩模对准中的滑移位错

    公开(公告)号：US5345310A

    公开(公告)日：1994-09-06

    申请号：US78878

    申请日：1993-06-15

    申请人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Joe Zelayeta

    发明人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Joe Zelayeta

    IPC分类号： G03F9/00 ,  G01B11/26

    CPC分类号： G03F9/7003 ,  G03F9/70

    摘要： Techniques for identifying and determining the orientation, magnitude, and direction of slip plane dislocations transecting semiconductor dies are described, whereby a four point alignment pattern is examined for "squareness" and size integrity. Lack of squareness or significant change in apparent size of various aspects of the alignment pattern indicate slip-plane dislocations. The magnitude, orientation and direction of the dislocations are determined geometrically from measurement of the alignment pattern. Various other aspects of the invention are directed to optimal alignment of a photolithographic mask to a die which has experienced a slip-plane dislocation, and to discrimination between slip-plane dislocation and die-site rotation.

    摘要翻译： 描述了用于识别和确定横切半导体管芯的滑移位错的取向，大小和方向的技术，由此检查四点对准图案的“矩形度”和尺寸完整性。 对准图案的各个方面的表观尺寸的平均度或显着变化的缺乏表示滑移位错。 位错的大小，取向和方向由对准图案的测量几何确定。 本发明的各种其它方面涉及光刻掩模与已经经历滑移位错的模具的最佳对准，以及滑移位错和模具位置旋转之间的区别。