公开(公告)号：US20240054070A1

公开(公告)日：2024-02-15

申请号：US18268292

申请日：2020-12-23

Applicant: Micron Technology, Inc

Inventor： Hua Tan ,  Zhen Shu ,  Nicola Colella

IPC: G06F12/02

CPC classification number: G06F12/0246

Abstract: A memory device comprises a memory array and a memory controller operatively coupled to the memory array. The memory controller includes a processor configured to initiate read operations to the memory array; compare the number of rad operations to a predetermined threshold number of read operations; initiate scanning memory pages of a block of memory cells for errors in response to reaching the threshold number of read operations for the block; and iteratively change the threshold number to a new threshold number, perform the new threshold number of read operations on the block of memory cells, and error scan memory pages associated with the last read operation of the new threshold number of rad operations.