公开(公告)号：US20230229556A1

公开(公告)日：2023-07-20

申请号：US17897048

申请日：2022-08-26

Applicant: Micron Technology, Inc.

Inventor： Patrick Estep ,  Steve Pawlowski ,  Emanuele Confalonieri ,  Nicola Del Gatto ,  Paolo Amato

IPC: G06F11/10

CPC classification number: G06F11/1076 ,  G06F2211/1009

Abstract: There are provided methods and systems for improving RAS features of a memory device. For example, there is provided a system that includes a memory and a memory side cache. The system further includes a processor that is configured to minimize accesses to the memory by executing certain operations. The operations can include computing a new parity based on old data, new data, and an old parity in response to data from the memory side cache being written to the memory.