公开(公告)号：US20180302073A1

公开(公告)日：2018-10-18

申请号：US15488545

申请日：2017-04-17

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Po-Yao Ko ,  Yi-Ming Wu

IPC: H03K5/156 ,  H03K5/05 ,  H03K5/00

Abstract: A duty cycle calibration circuit and a frequency synthesizer using the same are provided. The duty cycle calibration circuit includes a single-ended correction circuit and a single-ended detection circuit. The single-ended correction circuit is configured to adjust a duty cycle of an input clock signal. The single-ended correction circuit includes a first slew rate controller, a second slew rate controller, and at least one logic gate. The first slew rate controller adjusts a rising slew rate of an output clock signal in response to a control signal. The second slew rate controller adjusts a falling slew rate of the output clock signal in response to the control signal. The single-ended detection circuit is configured to detect a duty cycle of the output clock signal by converting the duty cycle of the output clock signal to an average voltage to be served as the control signal.

公开(公告)号：US10027280B1

公开(公告)日：2018-07-17

申请号：US15653519

申请日：2017-07-18

Applicant: Novatek Microelectronics Corp.

Inventor： Cheng-Dao Su ,  Chih-Hung Chen ,  Tzu-Cheng Yang ,  Yi-Ming Wu

IPC: H03K5/14 ,  H03B5/12 ,  H03K23/40 ,  H03K21/10 ,  H04B17/10

Abstract: An inductor-less local oscillator (LO) signal generation apparatus configured to generate one or more output signals which reduce a frequency pulling effect. The LO signal generation apparatus includes a multi-phase signal generation circuit, a phase signal generation circuit and one or more output circuits. The multi-phase signal generation circuit receives an input clock signal having a first frequency to generate a multi-phase clock signal. The multi-phase clock signal includes a plurality of clock signals each having the first frequency and different phases. The phase signal generation circuit is coupled to the multi-phase signal generation circuit to receive the multi-phase clock signal and output a plurality of phase signals indicating the phases of the clock signals. The one or more output circuits output the one or more output signals according to the clock signals and the phase signals without receiving feedback of any of the one or more output signals.