公开(公告)号：US5297255A

公开(公告)日：1994-03-22

申请号：US303626

申请日：1989-01-27

申请人： Naoko Hamanaka ,  Teruo Tanaka

发明人： Naoko Hamanaka ,  Teruo Tanaka

IPC分类号： G06F15/163 ,  G06F13/00

CPC分类号： G06F15/163

摘要： In a parallel computer, there are provided a plurality of processor elements 1-1 to 1-n) connected to each other by a network (2); each of said processor elements including a local memory (6) for holding a program and data related thereto, a processor (3) for performing an instruction in said program, a circuit (5) for transferring the data to the other processor elements, and a circuit (4) for receiving the data sent from the other processor element; a memory area (92:8) constructed of a plurality of reception data areas for temporarily storing data received by said receiving circuit, and a memory (92,8) constructed of a plurality of tag areas, provided for each of the reception data areas, for storing a valid data tag or an invalid data tag indicating that the data in the corresponding reception data area is valid or invalid; a transmitting circuit (5) for transmitting the data to be transmitted with attaching a data identifier predetermined by said data; a receiving circuit for writing the data into one of said plurality of reception data areas in response to the data received from said network, and writing the valid data tag into one of said plurality of reception data areas, said receiving circuit being parallel-operated with said processor; and, an access circuit (38) for reading both the data and tag from one of the reception data areas determined by said data identifier and from the corresponding tag areas in response to the data identifier designated by the instruction which is produced from said program for requiring the data reception, and for repeatedly reading the tag and data from the tag area and reception data area until the valid data tag is read out from the tag area in case that the read tag corresponds to the invalid data tag.

摘要翻译： 在并行计算机中，提供了由网络（2）彼此连接的多个处理器元件1-1至1-n）。 每个所述处理器元件包括用于保存程序的本地存储器（6）和与其相关的数据，用于在所述程序中执行指令的处理器（3），用于将数据传送到其他处理器元件的电路（5），以及 用于接收从另一个处理器元件发送的数据的电路（4）; 由用于临时存储由所述接收电路接收的数据的多个接收数据区域构成的存储区域（92：8），以及为每个接收数据区域提供的多个标签区域构成的存储器（92,8） 用于存储有效数据标签或指示相应接收数据区域中的数据有效或无效的无效数据标签; 发送电路（5），用于通过附加由所述数据预先确定的数据标识符发送要发送的数据; 接收电路，用于响应于从所述网络接收的数据将数据写入所述多个接收数据区域之一，并将有效数据标签写入所述多个接收数据区域之一，所述接收电路与 说处理器 以及访问电路（38），用于响应于由所述程序产生的指令指定的数据标识符，从由所述数据标识符确定的接收数据区域中的一个和相应的标签区域读取数据和标签， 需要数据接收，并且用于从标签区域和接收数据区域反复读取标签和数据，直到在读取标签对应于无效数据标签的情况下，从标签区域读出有效数据标签。