公开(公告)号：US5383188A

公开(公告)日：1995-01-17

申请号：US138006

申请日：1993-10-19

Applicant: Naoto Shigemoto

Inventor： Naoto Shigemoto

IPC: H04J3/06 ,  H04L7/00 ,  H04L7/04 ,  H04L7/10 ,  H04L25/40

CPC classification number: H04J3/06 ,  H04L7/10 ,  H04L7/0083 ,  H04L7/04

Abstract: A clock phase signal of each time slot of a TDM signal is stored into a corresponding memory location and a clock phase signal of a subsequent time slot is read from a memory location corresponding to the subsequent time slot for recovering clock pulses. A decoder is synchronized with the clock pulses for decoding an encoded digital signal of each time slot to produce a decoded signal. The error rate of the decoded signal of each time slot is detected and compared with a prescribed value. When the detected error rate is determined to be higher than the prescribed value, the write operation of the memory is disabled to prevent the clock phase signal stored in a memory location corresponding to the decoded signal from being overwritten with a subsequent clock phase signal.

Abstract translation: TDM信号的每个时隙的时钟相位信号被存储到对应的存储器位置中，并且从对应于后续时隙的存储器位置读取后续时隙的时钟相位信号，以恢复时钟脉冲。 解码器与用于解码每个时隙的编码数字信号的时钟脉冲同步以产生解码信号。 检测每个时隙的解码信号的错误率并将其与规定值进行比较。 当检测到的错误率被确定为高于规定值时，禁止存储器的写入操作，以防止存储在与解码信号相对应的存储器位置中的时钟相位信号被随后的时钟相位信号重写。