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    Automating photolithography in the fabrication of integrated circuits
    1.
    再颁专利
    Automating photolithography in the fabrication of integrated circuits 有权
    在制造集成电路时自动化光刻

    公开(公告)号：USRE38900E1

    公开(公告)日：2005-11-29

    申请号：US09273171

    申请日：1999-03-19

    申请人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Ashok K. Kapoor

    发明人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Ashok K. Kapoor

    IPC分类号： G03F7/20 ,  H01L21/66

    CPC分类号： G03F7/705 ,  G03F7/20 ,  G03F7/70433

    摘要： Automated photolithography of integrated circuit wafers is enabled with a processor connected to a Rayleigh derator, a form factor generator, a logic synthesizer, a layout generator, a lithography module and a wafer process. The Rayleigh derator receives manufacturing information resulting from yield data in the wafer process, and this manufacturing data is then used to derate the theoretical minimum feature size available for etching wafer masks given a known light source and object lens numerical aperture. This minimum feature size is then used by a form factor generator in sizing transistors in a net list to their smallest manufacturable size. A logic synthesizer then converts the net list into a physical design using a layout generator combined with user defined constraints. This physical design is then used by the mask lithography module to generate wafer masks for use in the semiconductor manufacturing. Manufacturing data including process and yield parameters is then transferred back to the Rayleigh processor for use in the designing of subsequent circuits. In this way, a direct coupling exists between the measurement of wafer process parameters and the automated sizing of semiconductor devices, enabling the production of circuits having the smallest manufacturable device sizes available for the given lithography and wafer process.

    摘要翻译： 集成电路晶片的自动光刻可通过连接到瑞利分离器，形状因子发生器，逻辑合成器，布局发生器，光刻模块和晶片工艺的处理器来实现。 Rayleigh变矩器接收由晶片工艺中的屈服数据产生的制造信息，然后使用该制造数据降低可用于蚀刻具有已知光源和物镜数值孔径的晶片掩模的理论最小特征尺寸。 然后，这种最小特征尺寸由形状因子发生器用于将网络列表中的晶体管调整到其最小可制造尺寸。 然后，逻辑合成器将网络列表转换为使用布局生成器与用户定义的约束组合的物理设计。 然后该掩模光刻模块将该物理设计用于半导体制造中使用的晶片掩模。 然后将包括处理和产量参数的制造数据传送回瑞利处理器，以用于后续电路的设计。 以这种方式，在晶片工艺参数的测量和半导体器件的自动化尺寸之间存在直接耦合，使得能够生产具有可用于给定光刻和晶片工艺的最小可制造器件尺寸的电路。

    Use of silicon for integrated circuit device interconnection by direct writing of patterns therein
    4.
    发明授权
    Use of silicon for integrated circuit device interconnection by direct writing of patterns therein 失效
    通过在其中直接写入图案，将硅用于集成电路器件互连

    公开(公告)号：US5721150A

    公开(公告)日：1998-02-24

    申请号：US614024

    申请日：1996-03-12

    申请人： Nicholas F. Pasch

    发明人： Nicholas F. Pasch

    IPC分类号： H01L21/268 ,  H01L21/3215 ,  H01L21/768 ,  H01L23/58 ,  H01L21/265

    CPC分类号： H01L23/573 ,  H01L21/2686 ,  H01L21/32155 ,  H01L21/76888 ,  H01L21/76894 ,  H01L2924/0002 ,  Y10S438/934

    摘要： An apparatus and method wherein conductive patterns are written in amorphous silicon or polysilicon deposited on an integrated circuit and used for interconnecting circuit elements contained therein. The substantially pure amorphous silicon or polysilicon is deposited onto an integrated circuit face at low temperature. A Focused Ion Beam deposition system deposits dopant atoms into the deposited pure silicon in a desired pattern. The dopant atoms are then activated by heat from a focused laser beam which adiabatically anneals the specifically doped areas of the deposited silicon. The resulting annealed doped areas of the silicon have low resistance suitable for circuit conductors. The surrounding undoped silicon reins a high resistance and a good insulator.

    摘要翻译： 一种其中导电图案被写入集成电路中沉积的非晶硅或多晶硅并用于互连其中包含的电路元件的装置和方法。 基本上纯的非晶硅或多晶硅在低温下沉积到集成电路面上。 聚焦离子束沉积系统以期望的图案将掺杂剂原子沉积到沉积的纯硅中。 然后，掺杂剂原子被来自聚焦激光束的热激活，该激光束绝热地退火沉积的硅的特定掺杂区域。 所得到的退火掺杂区域的硅具有适合于电路导体的低电阻。 周围的未掺杂硅可以获得高电阻和良好的绝缘体。

    Process for mounting a semiconductor device to a circuit substrate
    5.
    发明授权
    Process for mounting a semiconductor device to a circuit substrate 失效
    将半导体器件安装到电路基板的工艺

    公开(公告)号：US5700715A

    公开(公告)日：1997-12-23

    申请号：US434276

    申请日：1995-05-03

    申请人： Nicholas F. Pasch

    发明人： Nicholas F. Pasch

    IPC分类号： H01L21/60 ,  H01L23/532 ,  H01L21/283 ,  H01L21/58

    CPC分类号： H01L24/81 ,  H01L23/53285 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/81136 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01056 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/3025

    摘要： A process for mounting one or more dies a substrate, such as by ball-bumps. In one embodiment, a thin layer of heat-reflective material, such as gold, is disposed over the surface of the die facing the substrate, to shield the substrate from heat generated by the die. Other embodiments are directed to "pillar" spacers formed on the surface of the die and/or the substrate to control the spacing therebetween. The pillars can be thermally-conductive or thermally non-conductive. Thermally-conductive pillars can be thermally isolated from the die or substrate by an insulating layer. Thermally-conductive pillars can be employed to extract heat from selected areas of a die, into selected lines or areas of the substrate, and the heat on the substrate can then be dissipated by a coolant. Lines on the substrate which are advertently heated by the die can be employed to limit the current of selected circuits on the semiconductor die.

    摘要翻译： 用于将一个或多个模具安装在基板上的方法，例如通过球凸块。 在一个实施例中，诸如金的薄层的热反射材料设置在面对基板的模具的表面上，以屏蔽基板免受由模具产生的热量。 其他实施例涉及形成在管芯和/或衬底的表面上的“柱”间隔件，以控制它们之间的间隔。 支柱可以是导热的或热不导电的。 导热柱可以通过绝缘层与管芯或衬底热隔离。 可以使用导热柱将热量从模具的选定区域提取到基板的选定的线或区域中，然后基板上的热量可以被冷却剂消散。 通过裸片通常加热的衬底上的线可用于限制半导体管芯上所选电路的电流。

    Apparatus and method using optical energy for specifying and quantitatively controlling chemically-reactive components of semiconductor processing plasma etching gas
    6.
    发明授权
    Apparatus and method using optical energy for specifying and quantitatively controlling chemically-reactive components of semiconductor processing plasma etching gas 失效
    用于指定和定量控制半导体处理等离子体蚀刻气体的化学反应性组分的光能的装置和方法

    公开(公告)号：US5696428A

    公开(公告)日：1997-12-09

    申请号：US485517

    申请日：1995-06-07

    申请人： Nicholas F. Pasch

    发明人： Nicholas F. Pasch

    IPC分类号： C23C16/517 ,  H01J37/32 ,  H01J7/24

    CPC分类号： H01J37/321 ,  C23C16/517 ,  H01J37/32009 ,  H01J37/3233 ,  H01J37/32339

    摘要： An apparatus for producing a plasma suitable for semiconductor processing at pressures in the low millitorr range. The apparatus includes a vacuum chamber with a dielectric window, a generally planar coil disposed adjacent the window outside the chamber and coupled to an appropriate power source, and a plasma initiator disposed within the chamber. Once the plasma is initiated, the planar coil sustains the plasma by inductive power coupling. In one embodiment the plasma initiator is a secondary electrode disposed within the chamber and coupled to a second RF power source. In an alternative embodiment both the secondary electrode and a target pedestal are coupled to the secondary RF power source through a power splitter. In an alternative embodiment, the plasma initiator is used to ionize a portion of the process gas and provide a plasma that may then inductively couple with the planar coil. Initial ionization of the process gas may be achieved by use of an ultraviolet light source, an ultraviolet laser, a high voltage power source such as a tesla coil, or an electrical arc forming device such as a spark plug. A further aspect of the invention concerns introducing optical energy of preselected frequencies or wavelengths into a semiconductor processing plasma to induce changes in the composition or character of reactive species within the plasma.

    摘要翻译： 一种用于在低压力范围内的压力下生产适合半导体加工的等离子体的装置。 该设备包括具有电介质窗口的真空室，与室外的窗口相邻设置并且耦合到适当的电源的大致平面的线圈以及设置在室内的等离子体启动器。 一旦等离子体启动，平面线圈通过感应功率耦合来维持等离子体。 在一个实施例中，等离子体引发器是设置在室内并且耦合到第二RF电源的次级电极。 在替代实施例中，辅助电极和目标基座都通过功率分配器耦合到次级RF电源。 在替代实施例中，等离子体引发器用于电离一部分工艺气体并提供等离子体，其然后可以与平面线圈感应耦合。 处理气体的初始电离可以通过使用紫外光源，紫外激光器，诸如特斯拉线圈的高压电源或诸如火花塞的电弧形成装置来实现。 本发明的另一方面涉及将预选频率或波长的光能引入半导体处理等离子体以引起等离子体内的反应物质的组成或特性的变化。

    Process for performing low wavelength photolithography on semiconductor wafer using afocal concentration
    7.
    发明授权
    Process for performing low wavelength photolithography on semiconductor wafer using afocal concentration 失效
    使用无焦点浓度在半导体晶片上进行低波长光刻的工艺

    公开(公告)号：US5666189A

    公开(公告)日：1997-09-09

    申请号：US519797

    申请日：1995-08-28

    申请人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Joe Zelayeta

    发明人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Joe Zelayeta

    IPC分类号： G03F7/20 ,  G03B27/42

    CPC分类号： G03F7/70008 ,  G03F7/702 ,  G03F7/70375 ,  Y10S430/167

    摘要： Fine, sub-micron line features and patterns are created in a sensitized layer on a semiconductor wafer by a beam of low wavelength radiation, such as X-rays or Gamma-rays. A stream of such radiation is concentrated and collimated by a concentrator, the output of which is disposed in close proximity to the sensitized surface of the wafer. In this manner, the sensitized surface can be converted from one chemical state to another chemical state, essentially point-by-point. By moving one or the other of the beam or the wafer, line features can be converted in the sensitized surface. Typically, non-converted areas of the sensitized surface are removed, for further processing a layer underlying the sensitized surface. The concentrator is useful in for directing a stream of radiation from a continuously emitting source, such as from a pellet of Cobalt-60, onto the sensitized surface of the wafer when a shutter mechanism is incorporated either upstream (towards the source) or downstream (towards the wafer) from the concentrator.

    摘要翻译： 通过诸如X射线或γ射线的低波长辐射束在半导体晶片上的增感层中产生细微亚微米线特征和图案。 这种辐射流被集中器集中并准直，该集中器的输出设置在晶片敏感表面附近。 以这种方式，致敏表面可以从一个化学状态转变为另一个化学状态，基本上是逐点的。 通过移动光束或晶片中的一个或另一个，可以在致敏表面中转换线特征。 通常，去除敏化表面的未转化区域，以进一步处理敏化表面下面的层。 浓缩器可用于在将快门机构并入上游（朝向源）或下游（在源头）处引入来自连续发射源的辐射流，例如由钴-60颗粒沉积到晶片的致敏表面上（ 朝向晶片）。

    Depositing and densifying glass to planarize layers in semi-conductor devices based on CMOS structures
    9.
    发明授权
    Depositing and densifying glass to planarize layers in semi-conductor devices based on CMOS structures 失效
    沉积和致密化玻璃以基于CMOS结构在半导体器件中平坦化层

    公开(公告)号：US5514616A

    公开(公告)日：1996-05-07

    申请号：US278573

    申请日：1994-07-21

    申请人： Michael D. Rostoker ,  Nicholas F. Pasch

    发明人： Michael D. Rostoker ,  Nicholas F. Pasch

    IPC分类号： H01L21/266 ,  H01L21/3105 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/316

    CPC分类号： H01L21/31051 ,  H01L21/266 ,  H01L21/3105 ,  H01L21/31053 ,  H01L21/823871 ,  Y10S438/981

    摘要： Methods of planarizing one or more layers having an irregular top surface topology in a semiconductor device based on an underlying MOS structure are disclosed. Methods of creating doped wells or regions for the underlying MOS structure are also disclosed, using thick oxide growths on the surface of the substrate to mask implantation of ions into the wells. A technique for creating a pair of adjacent complementary oppositely-doped wells, such as for a CMOS structure, using a thick oxide growths as a mask is also disclosed. One of the methods of planarizing the one or more layers involves depositing, densifying and re-flowing a layer of glass on top of the topological layer. Another method of planarizing the one or more layers involves depositing, densifying and chemical-mechanically polishing the deposited and densified glass, thereby avoiding an additional temperature cycle (i.e., for re-flowing the glass) which would adversely affect underlying diffusions.

    摘要翻译： 公开了基于下面的MOS结构在半导体器件中平面化具有不规则顶表面拓扑的一个或多个层的方法。 还公开了为底层MOS结构产生掺杂阱或区域的方法，其使用在衬底表面上的厚氧化物生长来掩蔽将离子注入到阱中。 还公开了一种用于产生一对相邻的互补相对掺杂阱的技术，例如使用厚氧化物生长作为掩模的CMOS结构。 对一个或多个层进行平坦化的方法之一包括在拓扑层顶部沉积，致密化和再流动玻璃层。 平面化一个或多个层的另一种方法包括沉积，致密化和化学机械抛光沉积的和致密化的玻璃，从而避免对底层扩散产生不利影响的附加温度循环（即，用于重新流动玻璃）。

    Image masks for semiconductor lithography
    10.
    发明授权
    Image masks for semiconductor lithography 失效
    用于半导体光刻的图像掩模

    公开(公告)号：US5512395A

    公开(公告)日：1996-04-30

    申请号：US340251

    申请日：1994-11-16

    申请人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Joe Zelayeta

    发明人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Joe Zelayeta

    IPC分类号： G03F1/22 ,  G03F7/20 ,  G03F9/00

    CPC分类号： G03F1/22 ,  G03F7/2039

    摘要： Fine, sub-micron line features and patterns are created in a sensitized layer on a semiconductor wafer by a beam of low wavelength radiation, such as X-rays. The X-ray source emits very low wavelength radiation along a path towards a sensitized surface of a semiconductor wafer. An image mask substrate is disposed in the path of the radiation, and is provided with opaque material on a surface thereof, forming a pattern. The image mask is spaced sufficiently close to the wafer that radiation passing through the mask forms a corresponding pattern in the surface of the wafer. For X-ray radiation, the opaqueing material is gold, tungsten, platinum, barium, lead, iridium, rhodium, or the like.

    摘要翻译： 通过诸如X射线的低波长辐射束在半导体晶片上的增感层中产生细的亚微米线特征和图案。 X射线源沿着朝向半导体晶片的敏化表面的路径发射非常低的波长辐射。 图像掩模基板设置在辐射的路径中，并且在其表面上设置有不透明材料，形成图案。 图像掩模与晶片充分地间隔开，通过掩模的辐射在晶片表面形成相应的图案。 对于X射线辐射，不透明材料是金，钨，铂，钡，铅，铱，铑等。