公开(公告)号：US06694497B2

公开(公告)日：2004-02-17

申请号：US10010962

申请日：2001-10-26

Applicant: Nicholas Pavey

Inventor： Nicholas Pavey

IPC: G06F1750

CPC classification number: G01R31/318342 ,  G01R31/318513

Abstract: A method of testing integrated circuitry at a module and system level, in which an intermediate test, including multiple testing steps, is generated in a third programming language. The intermediate test is converted into an abstract representation of the testing steps. System and module level tests based on the abstract representation are generated in second and first respective programming languages. The integrated circuitry is then tested at system level with the system-level test and at module level with the module level test.

Abstract translation: 一种在模块和系统级别测试集成电路的方法，其中以第三编程语言生成包括多个测试步骤的中间测试。 中间测试被转换成测试步骤的抽象表示。 基于抽象表示的系统和模块级测试以第二和第一各自的编程语言生成。 然后在系统级别对系统级测试进行集成电路测试，并在模块级别进行模块级测试。

公开(公告)号：US07133817B2

公开(公告)日：2006-11-07

申请号：US10074265

申请日：2002-02-12

Applicant: Nicholas Pavey

Inventor： Nicholas Pavey

IPC: G06F17/50 ,  G06F9/45

CPC classification number: G06F17/5022

Abstract: A method of verifying a digital hardware design simulated in a hardware design language (HDL). States to be verified are defined, including signal values for each component within the hardware design. A test is applied to the hardware design, such that traces of internal signals within the hardware design are recorded. Each trace includes signal data, time data and at least the internal signals associated with the components. The traces are processed to ascertain whether the plurality of components simultaneously had the signal values associated with the state, thereby to ascertain whether the state was achieved.