公开(公告)号：US20210182656A1

公开(公告)日：2021-06-17

申请号：US17183720

申请日：2021-02-24

Applicant: OLYMPUS CORPORATION

Inventor： Hideaki Furukawa

IPC: G06N3/063 ,  G06F7/507 ,  G06F17/15

Abstract: In this arithmetic processing device, during a filter processing and a cumulative addition processing for calculating a specific pixel of an output feature amount map, an arithmetic controller controls so as to temporarily store an intermediate result in a cumulative addition result storing memory and process another pixel, store the intermediate result of the cumulative addition processing for all pixels in the cumulative addition result storing memory, then return to a first pixel, read the value stored in the cumulative addition result storing memory as an initial value of the cumulative addition processing, and continue the cumulative addition processing.

公开(公告)号：US20210117762A1

公开(公告)日：2021-04-22

申请号：US17132575

申请日：2020-12-23

Applicant: OLYMPUS CORPORATION

Inventor： Hideaki Furukawa

IPC: G06N3/063 ,  G06F7/57

Abstract: An SRAM write controller of an arithmetic processing device for deep learning, which performs a convolution processing and a full-connect processing, virtually divides each SRAM constituting a data storage memory into a plurality of areas, switches the area to be written by the ID and controls so that different input feature maps of the same coordinate are stored in the same SRAM, and controls such that different input feature value map data of the same coordinate is stored in the same SRAM.

公开(公告)号：US20150249790A1

公开(公告)日：2015-09-03

申请号：US14714915

申请日：2015-05-18

Applicant: OLYMPUS CORPORATION

Inventor： Nobuyuki WATANABE ,  Naoyuki Miyashita ,  Hideaki Furukawa ,  Hiroshi Matsuzaki ,  Takahiro Yano

IPC: H04N5/232 ,  G06K9/32 ,  H04N5/262

CPC classification number: H04N5/23293 ,  G06K9/00711 ,  G06K9/3233 ,  G06K2209/27 ,  H04N5/23219 ,  H04N5/2621

Abstract: An image processing apparatus receives an image signal and generates a display image having an image range associated with a display area of a display unit from an image based on the image signal. The image processing apparatus includes a position-of-interest-calculating-unit, a frame-out-accuracy-calculation-unit, an alteration-variable-decision-unit and an image-alteration-unit. The position-of-interest-calculating-unit calculates a position of interest as a position of an object of interest in the image. The frame-out-accuracy-calculation-unit calculates a frame-out accuracy representing an accuracy that the position of interest deviates from the image range based on the position of interest and the image range. The alteration-variable-decision-unit decides a processing variable of alteration processing performed with respect to the image in conformity with the frame-out accuracy. The image-alteration-unit performs the alteration processing with respect to the image in conformity with the decided processing variable to generate a signal of the display image.

Abstract translation: 图像处理设备接收图像信号，并且基于图像信号从图像生成具有与显示单元的显示区域相关联的图像范围的显示图像。 图像处理装置包括感兴趣位置计算单元，帧输出精度计算单元，变更判定单元和图像改变单元。 感兴趣位置计算单元计算感兴趣的位置作为图像中的感兴趣对象的位置。 帧输出精度计算单元基于感兴趣的位置和图像范围计算表示关注位置偏离图像范围的精度的帧输出精度。 改变判定单元根据帧输出精度来决定相对于图像执行的变更处理的处理变量。 图像改变单元根据所决定的处理变量执行关于图像的改变处理，以生成显示图像的信号。

公开(公告)号：US20220113944A1

公开(公告)日：2022-04-14

申请号：US17558783

申请日：2021-12-22

Applicant: OLYMPUS CORPORATION

Inventor： Hideaki Furukawa

IPC: G06F7/57 ,  G06F17/15

Abstract: In an arithmetic processing device, a controller includes: a second non-linear converter that, when a selector has branched off to a second processing side, performs non-linear arithmetic processing on the result of a cumulative addition processing of a first adder; and a second pooling processing part to which the results of the cumulative addition processing of k first adders that have been subject to the non-linear arithmetic processing by the second non-linear converter are inputted, the second pooling processing part performing a pooling process on the simultaneously inputted data. A data-storing memory manager writes the same data to k different data-storing memories when the number of input feature map data is less than or equal to N/k. The controller performs a control so that the selector branches off to the second processing side when the number of input feature map data is less than or equal to N/k.

公开(公告)号：US20210042616A1

公开(公告)日：2021-02-11

申请号：US17081006

申请日：2020-10-27

Applicant: OLYMPUS CORPORATION

Inventor： Hideaki Furukawa

IPC: G06N3/063 ,  G06N3/08 ,  G06F7/50 ,  G06F7/523 ,  G11C11/413

Abstract: An arithmetic part of an arithmetic processing device includes: a filter processing part that has a multiplier and a first adder and performs filter processing; a second adder that performs cumulative addition processing that cumulatively adds all of the results of the filter processing as executed in N parallel; a non-linear conversion part that performs non-linear arithmetic processing on the result of the cumulative addition processing; a pooling processing part that performs pooling processing on the result of the non-linear arithmetic processing; and an arithmetic control part that controls the filter processing part, the second adder, the non-linear conversion part, and the pooling processing part.

公开(公告)号：US12190227B2

公开(公告)日：2025-01-07

申请号：US17081006

申请日：2020-10-27

Applicant: OLYMPUS CORPORATION

Inventor： Hideaki Furukawa

IPC: G06N3/063 ,  G06F17/15 ,  G06N3/08 ,  G11C11/413

Abstract: An arithmetic part of an arithmetic processing device includes: a filter processing part that has a multiplier and a first adder and performs filter processing; a second adder that performs cumulative addition processing that cumulatively adds all of the results of the filter processing as executed in N parallel; a non-linear conversion part that performs non-linear arithmetic processing on the result of the cumulative addition processing; a pooling processing part that performs pooling processing on the result of the non-linear arithmetic processing; and an arithmetic control part that controls the filter processing part, the second adder, the non-linear conversion part, and the pooling processing part.

公开(公告)号：US12050985B2

公开(公告)日：2024-07-30

申请号：US17132575

申请日：2020-12-23

Applicant: OLYMPUS CORPORATION

Inventor： Hideaki Furukawa

IPC: G06F7/57 ,  G06N3/063 ,  G06N3/08

CPC classification number: G06N3/063 ,  G06F7/57 ,  G06N3/08

Abstract: An SRAM write controller of an arithmetic processing device for deep learning, which performs a convolution processing and a full-connect processing, virtually divides each SRAM constituting a data storage memory into a plurality of areas, switches the area to be written by the ID and controls so that different input feature maps of the same coordinate are stored in the same SRAM, and controls such that different input feature value map data of the same coordinate is stored in the same SRAM.

公开(公告)号：US09787905B2

公开(公告)日：2017-10-10

申请号：US14714915

申请日：2015-05-18

Applicant: OLYMPUS CORPORATION

Inventor： Nobuyuki Watanabe ,  Naoyuki Miyashita ,  Hideaki Furukawa ,  Hiroshi Matsuzaki ,  Takahiro Yano

IPC: H04N5/232 ,  H04N5/262 ,  G06K9/00 ,  G06K9/32

CPC classification number: H04N5/23293 ,  G06K9/00711 ,  G06K9/3233 ,  G06K2209/27 ,  H04N5/23219 ,  H04N5/2621

Abstract: An image processing apparatus receives an image signal and generates a display image having an image range associated with a display area of a display unit from an image based on the image signal. The image processing apparatus includes a position-of-interest-calculating-unit, a frame-out-accuracy-calculation-unit, an alteration-variable-decision-unit and an image-alteration-unit. The position-of-interest-calculating-unit calculates a position of interest as a position of an object of interest in the image. The frame-out-accuracy-calculation-unit calculates a frame-out accuracy representing an accuracy that the position of interest deviates from the image range based on the position of interest and the image range. The alteration-variable-decision-unit decides a processing variable of alteration processing performed with respect to the image in conformity with the frame-out accuracy. The image-alteration-unit performs the alteration processing with respect to the image in conformity with the decided processing variable to generate a signal of the display image.