公开(公告)号：US10275553B2

公开(公告)日：2019-04-30

申请号：US14155608

申请日：2014-01-15

Applicant: Oracle International Corporation

Inventor： Krishnan Sundaresan ,  Aravind Oommen ,  Mohd Jamil Mohd ,  Hemanga Lal Das ,  Pranjal Srivastava

IPC: G06F17/50

Abstract: A method for simulating a power consumption associated with a circuit. Once a netlist describing the circuit and an input stimulus for the netlist are obtained, the netlist is partitioned into multiple circuit blocks. Circuit logic models (CLMs) implemented in a hardware description language (HDL) are then obtained for the multiple circuit blocks and a logic netlist is generated from the multiple CLMs. A power vector for a CLM corresponding to a circuit block is calculated using a logic simulator inputting the logic netlist and the input stimulus. Further, a power consumption value is calculated for the circuit block using a circuit simulator and the power vector. The power consumption associated with the circuit is calculated based on the power consumption values for various circuit blocks.

公开(公告)号：US20150199460A1

公开(公告)日：2015-07-16

申请号：US14155608

申请日：2014-01-15

Applicant: Oracle International Corporation

Inventor： Krishnan Sundaresan ,  Aravind Oommen ,  Mohd Jamil Mohd ,  Hemanga Lal Das ,  Pranjal Srivastava

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F2217/78

Abstract: A method for simulating a power consumption associated with a circuit. The method includes: obtaining a netlist describing the circuit and an input stimulus for the netlist; partitioning the netlist into multiple circuit blocks; obtaining multiple circuit logic models (CLMs) implemented in a hardware description language (HDL) for the multiple circuit blocks; generating a logic netlist from the multiple CLMs; calculating, using a logic simulator inputting the logic netlist and the input stimulus, a power vector for a CLM corresponding to a first circuit block; calculating, using a circuit simulator and the power vector, a first power consumption value for the first circuit block; and calculating the power consumption associated with the circuit based on the first power consumption value.

Abstract translation: 一种用于模拟与电路相关联的功耗的方法。 该方法包括：获得描述电路的网表和网表的输入激励; 将网表划分成多个电路块; 获得用于多个电路块的硬件描述语言（HDL）中实现的多个电路逻辑模型（CLM）; 从多个CLM生成逻辑网表; 使用逻辑模拟器输入逻辑网表和输入激励来计算对应于第一电路块的CLM的功率矢量; 使用电路模拟器和功率矢量来计算第一电路块的第一功耗值; 以及基于所述第一功耗值计算与所述电路相关联的功耗。

公开(公告)号：US08751983B1

公开(公告)日：2014-06-10

申请号：US13789192

申请日：2013-03-07

Applicant: Oracle International Corporation

Inventor： Thomas Mitchell ,  Krishnan Sundaresan ,  Quan Tran ,  Yibin Xia

IPC: G06F17/50

CPC classification number: G06F17/5045

Abstract: A design partitioning method and apparatus includes an RTL reader module configured to receive, process, and parse hardware descriptive language of a circuit design; an expression graph module configured to trace identified signal dependencies to determine dependent elements along selected paths within the circuit design; a hierarchy flattener module configured to remove existing circuit design hierarchies based on the identified signal dependencies and determined dependent elements; a partition specification reader module that defines selected paths within the circuit design into a partition specification; a design partitioner module configured to separate the flattened circuit design hierarchy according to the partition specification; a re-partitioner module configured to create a second hierarchical circuit design structure based on the separated, flattened circuit design hierarchy that is behaviorally identical to the circuit design; and an RTL design write-out module configured to output the second hierarchical circuit design structure for analysis.

Abstract translation: 一种设计划分方法和装置，包括：RTL读取器模块，被配置为接收，处理和解析电路设计的硬件描述语言; 表示图模块，其被配置为跟踪所识别的信号依赖性以确定沿着所述电路设计内的选定路径的依赖元件; 层级平整器模块，被配置为基于所识别的信号依赖性和确定的依赖元素来去除现有的电路设计层级; 分区规范读取器模块，其将所述电路设计内的所选路径定义为分区规范; 设计分割器模块，被配置为根据分区规范分离扁平化的电路设计层级; 重新分割器模块，其被配置为基于与所述电路设计行为相同的分离的，扁平化的电路设计层级来创建第二分层电路设计结构; 以及被配置为输出用于分析的第二分层电路设计结构的RTL设计写出模块。