公开(公告)号：US08990280B2

公开(公告)日：2015-03-24

申请号：US11599106

申请日：2006-11-14

申请人： Partha Sriram ,  Robert Quan ,  Bhagawan Reddy Gnanapa ,  Ahmet Karakas

发明人： Partha Sriram ,  Robert Quan ,  Bhagawan Reddy Gnanapa ,  Ahmet Karakas

IPC分类号： G06F17/14 ,  G06F7/52 ,  G10L19/02 ,  G10L25/27

CPC分类号： G06F17/147 ,  G10L19/0212 ,  G10L25/27

摘要： In some embodiments, a data processing system including an operation unit including circuitry configurable to perform any selected one of a number of operations on data (e.g., audio data) and a configuration unit configured to assert configuration information to configure the operation unit to perform the selected operation. When the operation includes matrix multiplication of a data vector and a matrix whose coefficients exhibit symmetry, the configuration information preferably includes bits that determine signs of all but magnitudes of only a subset of the coefficients. When the operation includes successive addition and subtraction operations on operand pairs, the configuration information preferably includes bits that configure the operation unit to operate in an alternating addition/subtraction mode to perform successive addition and subtraction operations on each pair of data values of a sequence of data value pairs.

摘要翻译： 在一些实施例中，一种数据处理系统，包括操作单元，该操作单元包括可配置为执行对数据的多个操作（例如，音频数据）中的任何一个操作的配置单元，以及配置单元，用于断言配置信息，以配置操作单元执行 选择操作。 当操作包括数据向量的矩阵乘法和其系数表现出对称性的矩阵时，配置信息优选地包括仅确定系数的子集的除了大小的符号的位。 当操作包括对操作数对的连续加减运算时，配置信息优选地包括配置操作单元以交替加/减模式操作的位，以对序列的每一对数据值执行连续的加法和减法运算 数据值对。

公开(公告)号：US20070078661A1

公开(公告)日：2007-04-05

申请号：US11599106

申请日：2006-11-14

申请人： Partha Sriram ,  Robert Quan ,  Bhagawan Gnanapa ,  Ahmet Karakas

发明人： Partha Sriram ,  Robert Quan ,  Bhagawan Gnanapa ,  Ahmet Karakas

IPC分类号： G10L21/00

CPC分类号： G06F17/147 ,  G10L19/0212 ,  G10L25/27

摘要： In some embodiments, a data processing system including an operation unit including circuitry configurable to perform any selected one of a number of operations on data (e.g., audio data) and a configuration unit configured to assert configuration information to configure the operation unit to perform the selected operation. When the operation includes matrix multiplication of a data vector and a matrix whose coefficients exhibit symmetry, the configuration information preferably includes bits that determine signs of all but magnitudes of only a subset of the coefficients. When the operation includes successive addition and subtraction operations on operand pairs, the configuration information preferably includes bits that configure the operation unit to operate in an alternating addition/subtraction mode to perform successive addition and subtraction operations on each pair of data values of a sequence of data value pairs. In some embodiments, the configuration information includes bits that configure the operation unit to operate in a non-consecutive (e.g., butterfly or bit-reversed) addressing mode to access memory locations having consecutive addresses in a predetermined non-consecutive sequence. Other aspects are audio encoders and decoders including any embodiment of, and configuration units and operation units for use in, any embodiment of the system, and methods performed during operation of any embodiment of the system or configuration or operation unit thereof.

摘要翻译： 在一些实施例中，一种数据处理系统，包括操作单元，该操作单元包括可配置为执行对数据的多个操作（例如，音频数据）中的任何一个操作的配置单元，以及配置单元，用于断言配置信息，以配置操作单元执行 选择操作。 当操作包括数据向量的矩阵乘法和其系数表现出对称性的矩阵时，配置信息优选地包括仅确定系数的子集的除了大小的符号的位。 当操作包括对操作数对的连续加减运算时，配置信息优选地包括配置操作单元以交替加/减模式操作的位，以对序列的每一对数据值执行连续的加法和减法运算 数据值对。 在一些实施例中，配置信息包括配置操作单元以非连续（例如，蝶形或位反转）寻址模式操作以访问具有预定非连续序列中的连续地址的存储单元的位。 其他方面是音频编码器和解码器，包括用于系统的任何实施例的任何实施例，配置单元和操作单元，以及在系统或其配置或操作单元的任何实施例的操作期间执行的方法。

公开(公告)号：US07433981B1

公开(公告)日：2008-10-07

申请号：US11243292

申请日：2005-09-30

申请人： Robert Quan ,  Parthasarathy Sriram

发明人： Robert Quan ,  Parthasarathy Sriram

IPC分类号： G06F13/12 ,  G06F7/38

CPC分类号： G10L19/0212 ,  G06F17/147 ,  G10L25/27

摘要： An architecture is described, wherein an operation unit, such as an arithmetic unit, is used for performing a variety of repetitive tasks. The present invention includes embodiments and related methods for power and computationally efficiency in performing repetitive tasks. The system includes an operation unit and a configuration control unit that is in communication with a processor. The processor sends the configuration information to the configuration unit and the configuration unit provides configuration information to the operation unit. The method includes configuring the operation unit using the configuration unit based on the configuration information, retrieving data from a designated location upon which the operation unit operates, and producing a result that is formatted and send to a destination.

摘要翻译： 描述了一种架构，其中诸如算术单元的操作单元被用于执行各种重复任务。 本发明包括用于执行重复任务的功率和计算效率的实施例和相关方法。 该系统包括与处理器通信的操作单元和配置控制单元。 处理器将配置信息发送给配置单元，配置单元向操作单元提供配置信息。 该方法包括基于配置信息，使用配置单元配置操作单元，从操作单元操作的指定位置检索数据，并产生格式化并发送到目的地的结果。

公开(公告)号：US06922771B2

公开(公告)日：2005-07-26

申请号：US10131359

申请日：2002-04-24

申请人： Jason Seung-Min Kim ,  Robert Quan

发明人： Jason Seung-Min Kim ,  Robert Quan

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/30 ,  G06F9/302 ,  G06F9/38 ,  G06F13/40 ,  G06F15/76

CPC分类号： G06F9/3875 ,  G06F9/30014 ,  G06F9/30145

摘要： The present invention provides a vector floating point unit (FPU) comprising a product-terms bus, a summation bus, a plurality of FIFO (first in first out) registers, a crossbar operand multiplexor coupled, a floating point multiplier, and a floating point adder. The floating point multiplier and the floating point adder are disposed between the crossbar operand multiplexor and the product-terms and summation buses, and are in parallel to each other. The invention also provides the configuration register and the command register in order to provide flexible architecture and the capability to fine-tune the performance to a particular application. The invention performs the multiplication operation and the addition operation in a pipelined fashion. Once the pipeline is filled, the invention outputs one multiplication output and one addition output at each clock cycle. The invention reduces the latency of the pipelined operation and improves the overall system performance by separating the floating point multiplier from the floating point adder so that the multiplication operation can be executed separately and independently of the addition operation.

摘要翻译： 本发明提供了一种矢量浮点单元（FPU），其包括乘积项总线，求和总线，多个FIFO（先进先出）寄存器，交叉开关操作数多路复用器，浮点乘法器和浮点 加法器。 浮点乘法器和浮点加法器设置在交叉开关操作数多路复用器和乘积项和求和母线之间并且彼此并联。 本发明还提供了配置寄存器和命令寄存器，以便提供灵活的架构和将特性微调到特定应用的能力。 本发明以流水线方式执行乘法运算和加法运算。 一旦管道被填充，本发明在每个时钟周期输出一个乘法输出和一个相加输出。 本发明通过将浮点乘法器与浮点加法器分开来减少流水线操作的等待时间并提高整体系统性能，从而可以独立于加法运算执行乘法运算。