公开(公告)号：US08227264B2

公开(公告)日：2012-07-24

申请号：US13071894

申请日：2011-03-25

申请人： Paul S. Andry ,  Stephen L. Buchwalter ,  George A. Katopis ,  John U. Knickerbocker ,  Stelios G. Tsapepas ,  Bucknell C. Webb

发明人： Paul S. Andry ,  Stephen L. Buchwalter ,  George A. Katopis ,  John U. Knickerbocker ,  Stelios G. Tsapepas ,  Bucknell C. Webb

IPC分类号： H01L21/30

CPC分类号： H01L23/49827 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/00 ,  H01L2224/05552

摘要： An electronic device assembly is provided which includes a substrate, an interposer and an integrated circuit chip. The substrate is fabricated of a first material having a first thermal expansivity, and the interposer and integrated circuit chip are fabricated of a second material having a second thermal expansivity. The second thermal expansivity is different from the first thermal expansivity so that there is a coefficient of thermal expansion mismatch between the substrate and the interposer or chip. The interposer is coupled to the substrate via a first plurality of electrical contacts and an underfill adhesive at least partially surrounding the electrical contacts to bond the interposer to the substrate and thereby reduce strain on the first plurality of electrical contacts. The integrated circuit chip is coupled to the interposer via a second plurality of electrical contacts only, without use of an adhesive surrounding the second plurality of electrical contacts.

摘要翻译： 提供一种电子器件组件，其包括衬底，插入器和集成电路芯片。 衬底由具有第一热膨胀性的第一材料制成，并且插入器和集成电路芯片由具有第二热膨胀性的第二材料制成。 第二热膨胀性与第一热膨胀性不同，因此在衬底和插入件或芯片之间存在热膨胀失配系数。 插入器经由第一多个电触点和底部填充粘合剂耦合到基板，所述底部填充粘合剂至少部分地围绕电触点以将插入件结合到基板，从而减少第一多个电触点上的应变。 集成电路芯片仅通过第二多个电触点而耦合到插入器，而不使用围绕第二多个电触点的粘合剂。

公开(公告)号：US07936060B2

公开(公告)日：2011-05-03

申请号：US12431827

申请日：2009-04-29

申请人： Paul S. Andry ,  Stephen L. Buchwalter ,  George A. Katopis ,  John U. Knickerbocker ,  Stelios G. Tsapepas ,  Bucknell C. Webb

发明人： Paul S. Andry ,  Stephen L. Buchwalter ,  George A. Katopis ,  John U. Knickerbocker ,  Stelios G. Tsapepas ,  Bucknell C. Webb

IPC分类号： H01L23/52

CPC分类号： H01L23/49827 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/00 ,  H01L2224/05552

摘要： An electronic device assembly is provided which includes a substrate, an interposer and an integrated circuit chip. The substrate is fabricated of a first material having a first thermal expansivity, and the interposer and integrated circuit chip are fabricated of a second material having a second thermal expansivity. The second thermal expansivity is different from the first thermal expansivity so that there is a coefficient of thermal expansion mismatch between the substrate and the interposer or chip. The interposer is coupled to the substrate via a first plurality of electrical contacts and an underfill adhesive at least partially surrounding the electrical contacts to bond the interposer to the substrate and thereby reduce strain on the first plurality of electrical contacts. The integrated circuit chip is coupled to the interposer via a second plurality of electrical contacts only, without use of an adhesive surrounding the second plurality of electrical contacts.

摘要翻译： 提供一种电子器件组件，其包括衬底，插入器和集成电路芯片。 衬底由具有第一热膨胀性的第一材料制成，并且插入器和集成电路芯片由具有第二热膨胀性的第二材料制成。 第二热膨胀性与第一热膨胀性不同，因此在衬底和插入件或芯片之间存在热膨胀失配系数。 插入器经由第一多个电触点和底部填充粘合剂耦合到基板，所述底部填充粘合剂至少部分地围绕电触点以将插入件结合到基板，从而减少第一多个电触点上的应变。 集成电路芯片仅通过第二多个电触点而耦合到插入器，而不使用围绕第二多个电触点的粘合剂。

公开(公告)号：US10173888B2

公开(公告)日：2019-01-08

申请号：US15650788

申请日：2017-07-14

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  Bucknell C. Webb

发明人： Bucknell C. Webb

IPC分类号： B81B3/00 ,  B81C1/00 ,  G01R33/02 ,  G01R33/028 ,  H01H51/22

摘要： Deep via technology is used to construct an integrated silicon cantilever and cavity oriented in a vertical plane which creates an electrostatically-switched MEMS switch in a small wafer area. Another embodiment is a small wafer area electrostatically-switched, vertical-cantilever MEMS switch wherein the switch cavity is etched within a volume defined by walls grown internally within a silicon substrate using through vias.

公开(公告)号：US20170166438A1

公开(公告)日：2017-06-15

申请号：US14969329

申请日：2015-12-15

申请人： Bucknell C. Webb

发明人： Bucknell C. Webb

IPC分类号： B81B3/00 ,  B81C1/00

CPC分类号： B81B3/0056 ,  B81B2201/012 ,  B81B2201/014 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2203/04 ,  B81B2207/07 ,  B81C1/0015 ,  B81C1/00619 ,  B81C2201/0112 ,  B81C2201/0132 ,  B81C2201/0178 ,  B81C2203/0109 ,  B81C2203/0136 ,  H01H59/0009 ,  H01H2001/0078

摘要： Deep via technology is used to construct an integrated silicon cantilever and cavity oriented in a vertical plane which creates an electrostatically-switched MEMS switch in a small wafer area. Another embodiment is a small wafer area electrostatically-switched, vertical-cantilever MEMS switch wherein the switch cavity is etched within a volume defined by walls grown internally within a silicon substrate using through vias.

公开(公告)号：US20140013606A1

公开(公告)日：2014-01-16

申请号：US13567567

申请日：2012-08-06

申请人： Jae-Woong Nah ,  Katsuyuki Sakuma ,  Bucknell C. Webb

发明人： Jae-Woong Nah ,  Katsuyuki Sakuma ,  Bucknell C. Webb

IPC分类号： B43L7/00

CPC分类号： H01L21/50 ,  H01L21/561 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06582 ,  H01L2224/32145 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2224/81 ,  H01L2924/014

摘要： A template having tapered openings can be employed to enable injection of underfill material through gaps having a width less than a lateral dimension of an injector needle for the underfill material. Each tapered opening has a first lateral dimension on an upper side and a second lateral dimension on a lower side. Compliant material portions can be employed to accommodate variations in distance between the template and stacked semiconductor chips and/or an injector head. Optionally, another head can be employed to apply compressed gas to push out the underfill material after the underfill material is applied to the gaps. Multiple injector heads can be employed to simultaneously inject the underfill material at different sites. An adhesive layer can be substituted for the at least one lower compliant material portion.

摘要翻译： 可以使用具有锥形开口的模板，以使得能够通过具有小于底部填充材料的注射器针的横向尺寸的间隙的间隙注入底部填充材料。 每个锥形开口具有在上侧上的第一横向尺寸和在下侧上的第二横向尺寸。 可以采用符合材料的部分来适应模板和堆叠的半导体芯片和/或注射器头之间的距离的变化。 可选地，在将底部填充材料施加到间隙之后，可以使用另一个头部来施加压缩气体以推出底部填充材料。 可以使用多个注射器头来同时将底部填充材料注入不同的位置。 粘合剂层可以代替至少一个下顺应材料部分。

公开(公告)号：US08492901B2

公开(公告)日：2013-07-23

申请号：US12614062

申请日：2009-11-06

申请人： Bucknell C. Webb

发明人： Bucknell C. Webb

IPC分类号： H01L23/538

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

摘要： A structure includes a wafer having a top wafer surface. The wafer defines an opening. The top wafer surface defines a first reference direction perpendicular to the top wafer surface. The wafer has a thickness in the first reference direction. The structure also includes a through-wafer via formed in the opening. The through-wafer via has a shape, when viewed in a plane perpendicular to the first reference direction and parallel to the top wafer surface, of at least one of a spiral and a C-shape. The through-wafer via has a height in the first reference direction essentially equal to the thickness of the wafer in the first reference direction. Manufacturing techniques are also disclosed.

摘要翻译： 一种结构包括具有顶部晶片表面的晶片。 晶片限定开口。 顶部晶片表面限定垂直于顶部晶片表面的第一参考方向。 晶片具有第一基准方向的厚度。 该结构还包括形成在开口中的贯通晶片通孔。 当在垂直于第一参考方向的平面中观察并且平行于顶部晶片表面时，贯穿晶片通孔具有螺旋形和C形中的至少一种形状。 贯通晶片通孔的第一参考方向的高度基本上等于晶片在第一参考方向上的厚度。 还公开了制造技术。

公开(公告)号：US08487447B2

公开(公告)日：2013-07-16

申请号：US13111283

申请日：2011-05-19

申请人： Mario J. Interrante ,  Gary LaFontant ,  Michael J. Shapiro ,  Thomas A. Wassick ,  Bucknell C. Webb

发明人： Mario J. Interrante ,  Gary LaFontant ,  Michael J. Shapiro ,  Thomas A. Wassick ,  Bucknell C. Webb

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/3171 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02163 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05551 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/0569 ,  H01L2224/06131 ,  H01L2224/06134 ,  H01L2224/13005 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13026 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/049 ,  H01L2924/053 ,  H01L2224/05552

摘要： A semiconductor structure which includes a plurality of stacked semiconductor chips in a three dimensional configuration. There is a first semiconductor chip in contact with a second semiconductor chip. The first semiconductor chip includes a through silicon via (TSV) extending through the first semiconductor chip; an electrically conducting pad at a surface of the first semiconductor chip, the TSV terminating in contact at a first side of the electrically conducting pad; a passivation layer covering the electrically conducting pad, the passivation layer having a plurality of openings; and a plurality of electrically conducting structures formed in the plurality of openings and in contact with a second side of the electrically conducting pad, the contact of the plurality of electrically conducting structures with the electrically conducting pad being offset with respect to the contact of the TSV with the electrically conducting pad.

摘要翻译： 一种半导体结构，其包括三维结构中的多个层叠半导体芯片。 存在与第二半导体芯片接触的第一半导体芯片。 第一半导体芯片包括延伸穿过第一半导体芯片的贯穿硅通孔（TSV）; 在所述第一半导体芯片的表面处的导电焊盘，所述TSV终止于所述导电焊盘的第一侧接触; 覆盖所述导电焊盘的钝化层，所述钝化层具有多个开口; 以及形成在所述多个开口中并与所述导电垫的第二侧接触的多个导电结构，所述多个导电结构与所述导电垫的接触相对于所述TSV的接触而偏移 与导电垫。

公开(公告)号：US08385018B2

公开(公告)日：2013-02-26

申请号：US12611294

申请日：2009-11-03

申请人： Robert G. Biskeborn ,  Philipp Herget ,  Bucknell C. Webb

发明人： Robert G. Biskeborn ,  Philipp Herget ,  Bucknell C. Webb

IPC分类号： G11B5/265

CPC分类号： G11B5/3116 ,  G11B5/17 ,  G11B5/23 ,  G11B5/265 ,  G11B5/2652 ,  G11B5/59638

摘要： A magnetic device according to one embodiment includes a source of flux; a magnetic pole coupled to the source of flux, the magnetic pole having two or more gaps; and a low reluctance path positioned towards at least one of the gaps and not positioned towards at least one other of the gaps for affecting a magnetic field formed at the at least one of the gaps when the source of flux is generating flux. Other disclosed embodiments include devices having coil turns with a non-uniform placement in the magnetic yoke for altering a magnetic field formed at the at least one of the gaps during writing. In further embodiments, a geometry of the magnetic pole near or at one of the gaps is different than a geometry of the magnetic pole near or at another of the gaps to help equalize fields formed at the gaps when the source of flux is generating flux.

摘要翻译： 根据一个实施例的磁性装置包括通量源; 耦合到磁通源的磁极，所述磁极具有两个或更多个间隙; 以及朝向所述间隙中的至少一个定位的低磁阻路径，并且朝向所述间隙中的至少另一个定位，以在所述通量源产生磁通时影响形成在所述至少一个间隙处的磁场。 其他公开的实施例包括具有在磁轭中具有不均匀布置的线圈匝的装置，用于在写入期间改变在至少一个间隙处形成的磁场。 在另外的实施例中，靠近或在其中一个间隙处的磁极的几何形状不同于磁极在靠近或另一个间隙处的几何形状，以帮助当磁通源产生磁通时在间隙处形成的场均衡。

公开(公告)号：US20120292779A1

公开(公告)日：2012-11-22

申请号：US13111283

申请日：2011-05-19

申请人： MARIO J. INTERRANTE ,  Gary LaFontant ,  Michael J. Shapiro ,  Thomas A. Wassick ,  Bucknell C. Webb

发明人： MARIO J. INTERRANTE ,  Gary LaFontant ,  Michael J. Shapiro ,  Thomas A. Wassick ,  Bucknell C. Webb

IPC分类号： H01L23/48 ,  H01L21/28

CPC分类号： H01L23/3171 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02163 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05551 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/0569 ,  H01L2224/06131 ,  H01L2224/06134 ,  H01L2224/13005 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13026 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/049 ,  H01L2924/053 ,  H01L2224/05552

摘要： A semiconductor structure which includes a plurality of stacked semiconductor chips in a three dimensional configuration. There is a first semiconductor chip in contact with a second semiconductor chip. The first semiconductor chip includes a through silicon via (TSV) extending through the first semiconductor chip; an electrically conducting pad at a surface of the first semiconductor chip, the TSV terminating in contact at a first side of the electrically conducting pad; a passivation layer covering the electrically conducting pad, the passivation layer having a plurality of openings; and a plurality of electrically conducting structures formed in the plurality of openings and in contact with a second side of the electrically conducting pad, the contact of the plurality of electrically conducting structures with the electrically conducting pad being offset with respect to the contact of the TSV with the electrically conducting pad.

摘要翻译： 一种半导体结构，其包括三维结构中的多个层叠半导体芯片。 存在与第二半导体芯片接触的第一半导体芯片。 第一半导体芯片包括延伸穿过第一半导体芯片的贯穿硅通孔（TSV）; 在所述第一半导体芯片的表面处的导电焊盘，所述TSV终止于所述导电焊盘的第一侧接触; 覆盖所述导电焊盘的钝化层，所述钝化层具有多个开口; 以及形成在所述多个开口中并与所述导电垫的第二侧接触的多个导电结构，所述多个导电结构与所述导电垫的接触相对于所述TSV的接触而偏移 与导电垫。

公开(公告)号：US20110108958A1

公开(公告)日：2011-05-12

申请号：US12614062

申请日：2009-11-06

申请人： Bucknell C. Webb

发明人： Bucknell C. Webb

IPC分类号： H01L23/48 ,  H01L21/3205 ,  H01L21/768

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

摘要： A structure includes a wafer having a top wafer surface. The wafer defines an opening. The top wafer surface defines a first reference direction perpendicular to the top wafer surface. The wafer has a thickness in the first reference direction. The structure also includes a through-wafer via formed in the opening. The through-wafer via has a shape, when viewed in a plane perpendicular to the first reference direction and parallel to the top wafer surface, of at least one of a spiral and a C-shape. The through-wafer via has a height in the first reference direction essentially equal to the thickness of the wafer in the first reference direction. Manufacturing techniques are also disclosed.

摘要翻译： 一种结构包括具有顶部晶片表面的晶片。 晶片限定开口。 顶部晶片表面限定垂直于顶部晶片表面的第一参考方向。 晶片具有第一基准方向的厚度。 该结构还包括形成在开口中的贯通晶片通孔。 当在垂直于第一参考方向的平面中观察并且平行于顶部晶片表面时，贯穿晶片通孔具有螺旋形和C形中的至少一种形状。 贯通晶片通孔的第一参考方向的高度基本上等于晶片在第一参考方向上的厚度。 还公开了制造技术。