Glitch-free clock switching circuit
    1.
    发明授权
    Glitch-free clock switching circuit 有权
    无毛刺时钟切换电路

    公开(公告)号:US07554365B2

    公开(公告)日:2009-06-30

    申请号:US12045725

    申请日:2008-03-11

    IPC分类号: H03K17/00

    CPC分类号: G06F1/04

    摘要: A glitch-free clock switching circuit receives a first clock signal and a second clock signal and outputs a third clock signal corresponding to the first clock signal or a fourth clock signal corresponding to the second clock signal according to a clock switching signal. The glitch-free clock switching circuit switches to output clock signals by stopping output of a clock signal, and then waiting for a predetermined period of time before outputting another clock signal.

    摘要翻译: 无毛刺时钟切换电路接收第一时钟信号和第二时钟信号,并根据时钟切换信号输出与第一时钟信号对应的第三时钟信号或对应于第二时钟信号的第四时钟信号。 无毛刺时钟切换电路通过停止时钟信号的输出而切换为输出时钟信号,然后在输出另一个时钟信号之前等待预定的时间段。

    PRD (physical region descriptor) pre-fetch methods for DMA (direct memory access) units
    2.
    发明授权
    PRD (physical region descriptor) pre-fetch methods for DMA (direct memory access) units 有权
    用于DMA(直接存储器访问)单元的PRD(物理区域描述符)预取方法

    公开(公告)号:US09342472B2

    公开(公告)日:2016-05-17

    申请号:US11935429

    申请日:2007-11-06

    IPC分类号: G06F13/28 G06F12/08

    CPC分类号: G06F13/28 G06F12/0875

    摘要: PRD (Physical Region Descriptor) pre-fetch methods for DMA (Direct Memory Access) unit are provided. When a DMA out transaction for a memory is performed, it is determined whether a first queue is full or nearly full, wherein the first queue is used to store data corresponding to the DMA out transaction. If the first queue is full or nearly full, at least one PRD entry is read from a first PRD table, and stored to a first cache. When a DMA in transaction for the memory is performed, it is determined whether a second queue is empty or nearly empty, wherein the second queue is used to store data corresponding to the DMA in transaction. If the second queue is empty or nearly empty, at least one PRD entry is read from a second PRD table, and stored to a second cache.

    摘要翻译: 提供了用于DMA(直接存储器访问)单元的PRD(物理区域描述符)预取方法。 当执行用于存储器的DMA输出事务时,确定第一队列是否满或已满,其中第一队列用于存储对应于DMA输出事务的数据。 如果第一个队列已满或已满,则从第一个PRD表中读取至少一个PRD条目,并存储到第一个缓存。 当执行用于存储器的事务中的DMA时,确定第二队列是空还是几乎为空,其中第二队列用于在事务中存储对应于DMA的数据。 如果第二队列为空或几乎为空,则从第二PRD表读取至少一个PRD条目,并存储到第二高速缓存。

    PRD (PHYSICAL REGION DESCRIPTOR) PRE-FETCH METHODS FOR DMA (DIRECT MEMORY ACCESS) UNITS
    3.
    发明申请
    PRD (PHYSICAL REGION DESCRIPTOR) PRE-FETCH METHODS FOR DMA (DIRECT MEMORY ACCESS) UNITS 有权
    用于DMA(直接存储器访问)单元的PRE-FETCH方法(物理区域描述符)

    公开(公告)号:US20080320176A1

    公开(公告)日:2008-12-25

    申请号:US11935429

    申请日:2007-11-06

    IPC分类号: G06F13/28

    CPC分类号: G06F13/28 G06F12/0875

    摘要: PRD (Physical Region Descriptor) pre-fetch methods for DMA (Direct Memory Access) unit are provided. When a DMA out transaction for a memory is performed, it is determined whether a first queue is full or nearly full, wherein the first queue is used to store data corresponding to the DMA out transaction. If the first queue is full or nearly full, at least one PRD entry is read from a first PRD table, and stored to a first cache. When a DMA in transaction for the memory is performed, it is determined whether a second queue is empty or nearly empty, wherein the second queue is used to store data corresponding to the DMA in transaction. If the second queue is empty or nearly empty, at least one PRD entry is read from a second PRD table, and stored to a second cache.

    摘要翻译: 提供了用于DMA(直接存储器访问)单元的PRD(物理区域描述符)预取方法。 当执行用于存储器的DMA输出事务时,确定第一队列是否满或已满,其中第一队列用于存储对应于DMA输出事务的数据。 如果第一个队列已满或已满,则从第一个PRD表中读取至少一个PRD条目,并存储到第一个缓存。 当执行用于存储器的事务中的DMA时,确定第二队列是空还是几乎为空,其中第二队列用于在事务中存储对应于DMA的数据。 如果第二队列为空或几乎为空,则从第二PRD表读取至少一个PRD条目,并存储到第二高速缓存。

    GLITCH-FREE CLOCK SWITCHING CIRCUIT
    4.
    发明申请
    GLITCH-FREE CLOCK SWITCHING CIRCUIT 有权
    无刷时钟切换电路

    公开(公告)号:US20080258794A1

    公开(公告)日:2008-10-23

    申请号:US12045725

    申请日:2008-03-11

    IPC分类号: G06F1/04 H03K3/00

    CPC分类号: G06F1/04

    摘要: A glitch-free clock switching circuit receives a first clock signal and a second clock signal and outputs a third clock signal corresponding to the first clock signal or a fourth clock signal corresponding to the second clock signal according to a clock switching signal. The glitch-free clock switching circuit switches to output clock signals by stopping output of a clock signal, and then waiting for a predetermined period of time before outputting another clock signal.

    摘要翻译: 无毛刺时钟切换电路接收第一时钟信号和第二时钟信号,并根据时钟切换信号输出与第一时钟信号对应的第三时钟信号或对应于第二时钟信号的第四时钟信号。 无毛刺时钟切换电路通过停止时钟信号的输出而切换为输出时钟信号,然后在输出另一个时钟信号之前等待预定的时间段。

    UNIVERSAL SERIAL BUS HOST CONTROLLER AND CONTROL METHODS THEREOF
    5.
    发明申请
    UNIVERSAL SERIAL BUS HOST CONTROLLER AND CONTROL METHODS THEREOF 有权
    通用串行总线主机控制器及其控制方法

    公开(公告)号:US20090287871A1

    公开(公告)日:2009-11-19

    申请号:US12360123

    申请日:2009-01-27

    IPC分类号: G06F13/28

    CPC分类号: G06F13/385 G06F13/28

    摘要: The present invention provides a USB host controller and control method thereof. The USB host controller comprises a first controller, a second controller and a first memory. The first controller controls first transfer between a host and a USB device. The second controller controls second transfer between the host and the USB device. The first memory is coupled to the first controller and the second controller and is configured to temporarily store data transferred between the host and the USB device. The first controller accesses the first memory during the first transfer, and the second controller accesses the first memory during the second transfer.

    摘要翻译: 本发明提供一种USB主机控制器及其控制方法。 USB主机控制器包括第一控制器,第二控制器和第一存储器。 第一个控制器控制主机和USB设备之间的第一次传输。 第二个控制器控制主机和USB设备之间的第二次传输。 第一存储器耦合到第一控制器和第二控制器,并且被配置为临时存储在主机和USB设备之间传送的数据。 第一控制器在第一传送期间访问第一存储器,并且第二控制器在第二传送期间访问第一存储器。

    Electric fan
    6.
    外观设计

    公开(公告)号:USD542906S1

    公开(公告)日:2007-05-15

    申请号:US29252704

    申请日:2006-01-25

    申请人: Dejian Li

    设计人: Dejian Li

    SYSTEM AND METHOD FOR TESTING GAS MIGRATION PROCESS IN COAL-ROCK MASS
    7.
    发明申请
    SYSTEM AND METHOD FOR TESTING GAS MIGRATION PROCESS IN COAL-ROCK MASS 有权
    用于测试煤岩质量气体移动过程的系统和方法

    公开(公告)号:US20120118041A1

    公开(公告)日:2012-05-17

    申请号:US13386050

    申请日:2010-07-15

    IPC分类号: G01N30/02 G01N7/00

    摘要: A system and method for testing gas migration process in the coal and rock mass are disclosed. The method includes the following steps: selecting a cylindrical coal sample, applying an axial pressure and a radial pressure to the coal sample under a sealing state, and/or increasing temperature, to desorb gas absorbed by the coal sample; guiding the gas desorbed from the coal sample by a guiding passage, detecting gas flow rate and pressure, analyzing gas composition and content, and achieving a data statistics. The method provides a theory and data basis for researching the forming and occurring process of gas outburst accident in coal mine. The system is simple and easy to use, and is suitable for migration research of the gas absorbed in the deep coal-rock mass.

    摘要翻译: 公开了一种用于测试煤和岩体中气体迁移过程的系统和方法。 该方法包括以下步骤:选择圆柱形煤样,在密封状态和/或升高温度下向煤样施加轴向压力和径向压力,以解吸煤样吸收的气体; 通过引导通道引导从煤样中解吸的气体,检测气体流量和压力,分析气体组成和含量,并实现数据统计。 该方法为煤矿瓦斯突出事故形成和发生过程的研究提供了理论和数据依据。 该系统简单易用,适用于深层煤岩吸收气体的迁移研究。

    Electric fan
    8.
    外观设计

    公开(公告)号:USD554748S1

    公开(公告)日:2007-11-06

    申请号:US29252687

    申请日:2006-01-25

    申请人: Dejian Li

    设计人: Dejian Li

    Electric fan
    9.
    外观设计
    Electric fan 有权
    电扇

    公开(公告)号:USD540936S1

    公开(公告)日:2007-04-17

    申请号:US29252721

    申请日:2006-01-25

    申请人: Dejian Li

    设计人: Dejian Li

    DATA TRANSMISSION METHODS
    10.
    发明申请
    DATA TRANSMISSION METHODS 有权
    数据传输方法

    公开(公告)号:US20080244132A1

    公开(公告)日:2008-10-02

    申请号:US11693752

    申请日:2007-03-30

    申请人: Dejian Li Wenbin Li

    发明人: Dejian Li Wenbin Li

    IPC分类号: G06F13/00

    CPC分类号: G06F13/28

    摘要: Data transmission systems and methods. The data transmission system comprises a bus, a slave, a master, and a master interface. The master transmits a request comprising transfer information comprising a start address and a length. The master interface receives the request from the master. The master interface determines a burst type of a first burst according to the transfer information, and transmits the first burst with the burst type to the slave via the bus, where the first burst is aligned to at least one address boundary of the slave. The master interface receives data corresponding to the first burst from the slave, and transmits the data to the master.

    摘要翻译: 数据传输系统和方法。 数据传输系统包括总线,从机,主机和主机接口。 主机发送包括包括起始地址和长度的传输信息的请求。 主接口从主机接收请求。 主接口根据传输信息确定突发类型的第一突发,并且经由总线将具有突发类型的第一突发发送到从机,其中第一突发与从机的至少一个地址边界对准。 主接口从从站接收与第一个突发相对应的数据,并将数据发送给主设备。