公开(公告)号：US08299567B2

公开(公告)日：2012-10-30

申请号：US12952317

申请日：2010-11-23

申请人： Ping-Chuan Wang ,  Chunyan E Tian ,  Ronald Filippi ,  Wai-kin Li

发明人： Ping-Chuan Wang ,  Chunyan E Tian ,  Ronald Filippi ,  Wai-kin Li

IPC分类号： H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： Structures of electronic fuses (e-fuse) are provided. An un-programmed e-fuse includes a via of a first conductive material having a bottom and sidewalls with a portion of the sidewalls being covered by a conductive liner and the bottom of the via being formed on top of a dielectric layer, and a first and a second conductive path of a second conductive material formed on top of the dielectric layer with the first and second conductive paths being conductively connected through, and only through, the via at the sidewalls. A programmed e-fuse includes a via; a first conductive path at a first side of the via and being separated from sidewalls of the via by a void; and a second conductive path at a second different side of the via and being in conductive contact with the via through sidewalls of the via.

摘要翻译： 提供电子保险丝（e-fuse）的结构。 未编程的电子熔断器包括具有底部和侧壁的第一导电材料的通孔，侧壁的一部分被导电衬垫覆盖，并且通孔的底部形成在电介质层的顶部上，并且第一 以及形成在电介质层顶部上的第二导电材料的第二导电路径，其中第一和第二导电路径通过侧壁导通地连接，并且仅通过通孔。 编程的电子熔丝包括通孔; 在通孔的第一侧处的第一导电路径，并且通过空隙与通路的侧壁分离; 以及在所述通孔的第二不同侧的第二导电路径，并且与通孔通过所述通孔的侧壁导电接触。

公开(公告)号：US20120126363A1

公开(公告)日：2012-05-24

申请号：US12952317

申请日：2010-11-23

申请人： Ping-Chuan Wang ,  Chunyan E. Tian ,  Ronald Filippi ,  Wai-ki Li

发明人： Ping-Chuan Wang ,  Chunyan E. Tian ,  Ronald Filippi ,  Wai-ki Li

IPC分类号： H01L23/525

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： Structures of electronic fuses (e-fuse) are provided. An un-programmed e-fuse includes a via of a first conductive material having a bottom and sidewalls with a portion of the sidewalls being covered by a conductive liner and the bottom of the via being formed on top of a dielectric layer, and a first and a second conductive path of a second conductive material formed on top of the dielectric layer with the first and second conductive paths being conductively connected through, and only through, the via at the sidewalls. A programmed e-fuse includes a via; a first conductive path at a first side of the via and being separated from sidewalls of the via by a void; and a second conductive path at a second different side of the via and being in conductive contact with the via through sidewalls of the via.

摘要翻译： 提供电子保险丝（e-fuse）的结构。 未编程的电子熔断器包括具有底部和侧壁的第一导电材料的通孔，侧壁的一部分被导电衬垫覆盖，并且通孔的底部形成在电介质层的顶部上，并且第一 以及形成在电介质层顶部上的第二导电材料的第二导电路径，其中第一和第二导电路径通过侧壁导通地连接，并且仅通过通孔。 编程的电子熔丝包括通孔; 在通孔的第一侧处的第一导电路径，并且通过空隙与通路的侧壁分离; 以及在所述通孔的第二不同侧的第二导电路径，并且与通孔通过所述通孔的侧壁导电接触。

公开(公告)号：US08349723B2

公开(公告)日：2013-01-08

申请号：US13342221

申请日：2012-01-03

申请人： Ronald Filippi ,  Wai-kin Li ,  Ping-Chuan Wang

发明人： Ronald Filippi ,  Wai-kin Li ,  Ping-Chuan Wang

IPC分类号： H01L21/4763

CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76847 ,  H01L21/76852 ,  H01L23/5286 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： An embodiment of the invention provides a semiconductor structure, which may include a stud of a first conductive material formed inside a dielectric layer; a via of a second conductive material having a bottom and sidewalls with the bottom and the sidewalls being covered by a conductive liner, and the bottom being formed directly on top of the stud and being in contact with the via through the conductive liner; and one or more conductive paths of a third conductive material connecting to the via through the conductive liner at the sidewalls of said the. A method of making the semiconductor structure is also provided.

摘要翻译： 本发明的一个实施例提供一种半导体结构，其可以包括形成在电介质层内部的第一导电材料的支柱; 具有底部的第二导电材料的通孔和具有底部的侧壁，并且侧壁被导电衬垫覆盖，并且底部直接形成在螺柱的顶部上并且通过导电衬套与通孔接触; 以及一个或多个第三导电材料的导电路径，所述第三导电材料在所述导电衬套的侧壁处通过所述导电衬套连接到所述通孔。 还提供了制造半导体结构的方法。

公开(公告)号：US08164190B2

公开(公告)日：2012-04-24

申请号：US12491372

申请日：2009-06-25

申请人： Ronald Filippi ,  Wai-kin Li ,  Ping-Chuan Wang

发明人： Ronald Filippi ,  Wai-kin Li ,  Ping-Chuan Wang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76847 ,  H01L21/76852 ,  H01L23/5286 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： An embodiment of the invention provides a semiconductor structure, which may include a stud of a first conductive material formed inside a dielectric layer; a via of a second conductive material having a bottom and sidewalls with the bottom and the sidewalls being covered by a conductive liner, and the bottom being formed directly on top of the stud and being in contact with the via through the conductive liner; and one or more conductive paths of a third conductive material connecting to the via through the conductive liner at the sidewalls of said the. A method of making the semiconductor structure is also provided.

摘要翻译： 本发明的一个实施例提供一种半导体结构，其可以包括形成在电介质层内部的第一导电材料的支柱; 具有底部的第二导电材料的通孔和具有底部的侧壁，并且侧壁被导电衬垫覆盖，并且底部直接形成在螺柱的顶部上并且通过导电衬套与通孔接触; 以及一个或多个第三导电材料的导电路径，所述第三导电材料在所述导电衬套的侧壁处通过导电衬套连接到通孔。 还提供了制造半导体结构的方法。

公开(公告)号：US20100327445A1

公开(公告)日：2010-12-30

申请号：US12491372

申请日：2009-06-25

申请人： Ronald Filippi ,  Wai-kin Li ,  Ping-Chuan Wang

发明人： Ronald Filippi ,  Wai-kin Li ,  Ping-Chuan Wang

IPC分类号： H01L23/535 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76847 ,  H01L21/76852 ,  H01L23/5286 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： An embodiment of the invention provides a semiconductor structure, which may include a stud of a first conductive material formed inside a dielectric layer; a via of a second conductive material having a bottom and sidewalls with the bottom and the sidewalls being covered by a conductive liner, and the bottom being formed directly on top of the stud and being in contact with the via through the conductive liner; and one or more conductive paths of a third conductive material connecting to the via through the conductive liner at the sidewalls of said the. A method of making the semiconductor structure is also provided.

摘要翻译： 本发明的一个实施例提供一种半导体结构，其可以包括形成在电介质层内部的第一导电材料的支柱; 具有底部的第二导电材料的通孔和具有底部的侧壁，并且侧壁被导电衬垫覆盖，并且底部直接形成在螺柱的顶部上并且通过导电衬套与通孔接触; 以及一个或多个第三导电材料的导电路径，所述第三导电材料在所述导电衬套的侧壁处通过所述导电衬套连接到所述通孔。 还提供了制造半导体结构的方法。

公开(公告)号：US20120100712A1

公开(公告)日：2012-04-26

申请号：US13342221

申请日：2012-01-03

申请人： Ronald Filippi ,  Wai-kin Li ,  Ping-Chuan Wang

发明人： Ronald Filippi ,  Wai-kin Li ,  Ping-Chuan Wang

IPC分类号： H01L21/76

CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76847 ,  H01L21/76852 ,  H01L23/5286 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： An embodiment of the invention provides a semiconductor structure, which may include a stud of a first conductive material formed inside a dielectric layer; a via of a second conductive material having a bottom and sidewalls with the bottom and the sidewalls being covered by a conductive liner, and the bottom being formed directly on top of the stud and being in contact with the via through the conductive liner; and one or more conductive paths of a third conductive material connecting to the via through the conductive liner at the sidewalls of said the. A method of making the semiconductor structure is also provided.

摘要翻译： 本发明的一个实施例提供一种半导体结构，其可以包括形成在电介质层内部的第一导电材料的支柱; 具有底部的第二导电材料的通孔和具有底部的侧壁，并且侧壁被导电衬垫覆盖，并且底部直接形成在螺柱的顶部上并且通过导电衬套与通孔接触; 以及一个或多个第三导电材料的导电路径，所述第三导电材料在所述导电衬套的侧壁处通过所述导电衬套连接到所述通孔。 还提供了制造半导体结构的方法。

公开(公告)号：US07671444B2

公开(公告)日：2010-03-02

申请号：US11767580

申请日：2007-06-25

申请人： Ping-Chuan Wang ,  Wai-Kin Li

发明人： Ping-Chuan Wang ,  Wai-Kin Li

IPC分类号： H01L23/525 ,  H01L23/58 ,  H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： The disclosure relates generally to integrated circuit (IC) chip fabrication, and more particularly, to an e-fuse device including an opening, a first via and a second via in an interlayer dielectric, wherein the opening, the first via and the second via are connected to an interconnect below the interlayer dielectric; a dielectric layer that encloses the first via and the second via; and a metal layer over the dielectric layer, wherein the metal layer fills the opening with a metal, and wherein the first via and the second via are substantially empty to allow for electromigration of the interconnect during re-programming of the e-fuse device.

摘要翻译： 本公开总体上涉及集成电路（IC）芯片制造，更具体地，涉及包括开口，层间电介质中的第一通孔和第二通孔的电熔丝装置，其中开口，第一通孔和第二通孔 连接到层间电介质下面的互连; 包围第一通孔和第二通孔的电介质层; 以及在所述介电层上的金属层，其中所述金属层用金属填充所述开口，并且其中所述第一通孔和所述第二通孔基本为空，以允许在所述电熔丝装置的重新编程期间所述互连件的电迁移。

公开(公告)号：US08535991B2

公开(公告)日：2013-09-17

申请号：US12688254

申请日：2010-01-15

申请人： Kaushik Chanda ,  Lynne M. Gignac ,  Wai-Kin Li ,  Ping-Chuan Wang

发明人： Kaushik Chanda ,  Lynne M. Gignac ,  Wai-Kin Li ,  Ping-Chuan Wang

IPC分类号： H01L21/82

CPC分类号： G11C17/16 ,  H01L21/7682 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.

摘要翻译： 一种电可重新编程的保险丝，其包括设置在电介质材料中的互连，布置在所述互连的第一端的感测线，布置在所述互连的第二端的第一编程线，以及设置在所述互连的第二端的第二编程线 其中当从所述第一编程线通过所述互连件施加第一定向电子线到所述第二编程线时，所述保险丝可操作以在所述互连和感测线之间的界面处形成表面空隙，并且其中，所述保险丝是 当从所述第二编程线通过所述互连件施加第二编程线到所述第一编程线时，还可操作以治愈所述互连和所述感测线之间的表面空隙。

公开(公告)号：US20130233608A1

公开(公告)日：2013-09-12

申请号：US13414825

申请日：2012-03-08

申请人： Kai D. Feng ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Zhijian Yang

发明人： Kai D. Feng ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Zhijian Yang

IPC分类号： H05K1/11 ,  B05D5/12 ,  B05D5/00

CPC分类号： H01L23/5222 ,  H01L21/0274 ,  H01L21/3212 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H04L9/3278 ,  H04L2209/12 ,  H05K1/0289 ,  Y10T29/49117 ,  Y10T29/49165 ,  H01L2924/00

摘要： A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.

摘要翻译： 一种用于制造互连功能阵列的方法包括在衬底上形成第一多条导线，在第一多条导线和衬底之上形成绝缘体层，去除绝缘体层的部分以限定暴露在绝缘体层中的空腔 衬底和第一多个导电线的部分，其中去除绝缘体层的部分导致暴露衬底和第一多个导电线的部分的空腔的基本上随机的排列，在腔中沉积导电材料 并且在所述空腔和所述绝缘体层中的所述导电材料的部分上形成第二多个导电线。

公开(公告)号：US20120156450A1

公开(公告)日：2012-06-21

申请号：US13406965

申请日：2012-02-28

申请人： Wu-Song Huang ,  Wai-kin Li ,  Ping-Chuan Wang

发明人： Wu-Song Huang ,  Wai-kin Li ,  Ping-Chuan Wang

IPC分类号： B32B3/00

CPC分类号： G03F7/70466 ,  Y10S438/947 ,  Y10S438/948 ,  Y10T428/24802

摘要： A stack of a second photoresist having a second photosensitivity and a first photoresist having a first photosensitivity, which is greater than second photosensitivity, is formed on a substrate. A first pattern is formed in the first photoresist by a first exposure and a first development, while the second photoresist underneath remains intact. A second pattern comprising an array of lines is formed in the second photoresist. An exposed portion of the second photoresist underneath a remaining portion of the first photoresist forms a narrow portion of a line pattern, while an exposed portion of the second photoresist outside the area of the remaining portions of the photoresist forms a wide portion of the line pattern. Each wide portion of the line pattern forms a bulge in the second pattern, which increases overlay tolerance between the second pattern and the pattern of conductive vias.

摘要翻译： 在基板上形成具有第二感光性的第二光致抗蚀剂的叠层和具有大于第二光敏性的第一光敏性的第一光致抗蚀剂。 通过第一曝光和第一显影在第一光致抗蚀剂中形成第一图案，而下面的第二光致抗蚀剂保持完整。 在第二光致抗蚀剂中形成包括线阵列的第二图案。 在第一光致抗蚀剂的剩余部分下面的第二光致抗蚀剂的暴露部分形成线图案的窄部分，而在光致抗蚀剂的剩余部分的区域外的第二光致抗蚀剂的暴露部分形成线图案的宽部分 。 线图案的每个宽部分在第二图案中形成凸起，这增加了第二图案和导电通孔图案之间的覆盖公差。