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    Digital PVT compensation for delay chain
    1.
    发明授权
    Digital PVT compensation for delay chain 有权
    数字PVT补偿延时链

    公开(公告)号：US08680905B1

    公开(公告)日：2014-03-25

    申请号：US13486670

    申请日：2012-06-01

    申请人： Pradeep Nagarajan ,  Yan Chong ,  Sean Shau-Tu Lu ,  Chiakang Sung ,  Joseph Huang

    发明人： Pradeep Nagarajan ,  Yan Chong ,  Sean Shau-Tu Lu ,  Chiakang Sung ,  Joseph Huang

    IPC分类号： H03L7/00

    CPC分类号： H03L7/00 ,  G11C7/04 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254 ,  H03L7/0805 ,  H03L7/0812

    摘要： A circuit includes a delay locked loop (DLL), a calibration circuit and an output delay chain controlled by the calibration circuit. The DLL comprises a plurality of series-coupled first delay elements each of which has substantially the same first delay. The calibration circuit comprises a plurality of series-coupled second delay elements, each of which has substantially the same second delay that is less than the first delay, a first delay element, and a circuit for determining the minimum number of second delay elements that are needed to produce the first delay. The output delay chain comprises a plurality of series-coupled second delay elements, an input for receiving the input signal, and a circuit for selectively tapping the output delay chain at a plurality of taps in the output delay chain so as to produce in the input signal different delays of integral multiples of the second delay.

    摘要翻译： 电路包括由校准电路控制的延迟锁定环（DLL），校准电路和输出延迟链。 该DLL包括多个串联耦合的第一延迟元件，每个延迟元件具有基本上相同的第一延迟。 校准电路包括多个串联耦合的第二延迟元件，每个延迟元件具有基本相同的第二延迟小于第一延迟，第一延迟元件和用于确定第二延迟元件的最小数量的电路 需要产生第一个延迟。 输出延迟链包括多个串联耦合的第二延迟元件，用于接收输入信号的输入端和用于在输出延迟链中的多个抽头处有选择地分接输出延迟链的电路，以便产生输入 发出第二延迟的整数倍的不同延迟。

    Techniques for generating PVT compensated phase offset to improve accuracy of a locked loop
    2.
    发明授权
    Techniques for generating PVT compensated phase offset to improve accuracy of a locked loop 有权
    用于产生PVT补偿相位偏移以提高锁定环路精度的技术

    公开(公告)号：US08237475B1

    公开(公告)日：2012-08-07

    申请号：US12248031

    申请日：2008-10-08

    申请人： Pradeep Nagarajan ,  Sean Shau-Tu Lu ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong

    发明人： Pradeep Nagarajan ,  Sean Shau-Tu Lu ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0805 ,  H03L7/0814 ,  H03L7/0816

    摘要： A circuit includes a locked loop and a phase offset circuit. The locked loop generates first control signals for controlling a first delay in the locked loop. The phase offset circuit delays an input signal by a second delay that is controlled by second control signals to generate a delayed signal. The phase offset circuit generates the second control signals by adjusting the first control signals to increase the accuracy of the delayed signal with respect to a target phase. The second control signals compensate for at least a portion of a change in the second delay that is caused by a variation in at least one of a process, a supply voltage, and a temperature of the circuit.

    摘要翻译： 电路包括锁定环和相位偏移电路。 锁定环产生用于控制锁定环路中的第一延迟的第一控制信号。 相位偏移电路延迟由第二控制信号控制的第二延迟的输入信号以产生延迟的信号。 相位偏移电路通过调整第一控制信号来产生第二控制信号，以提高相对于目标相位的延迟信号的精度。 第二控制信号补偿由电路的过程，电源电压和温度中的至少一个的变化引起的第二延迟的变化的至少一部分。

    Circuit design technique for DQS enable/disable calibration
    3.
    发明授权
    Circuit design technique for DQS enable/disable calibration 有权
    DQS的电路设计技术启用/禁用校准

    公开(公告)号：US08787097B1

    公开(公告)日：2014-07-22

    申请号：US13250155

    申请日：2011-09-30

    申请人： Yan Chong ,  Joseph Huang ,  Sean Shau-Tu Lu ,  Pradeep Nagarajan ,  Chiakang Sung

    发明人： Yan Chong ,  Joseph Huang ,  Sean Shau-Tu Lu ,  Pradeep Nagarajan ,  Chiakang Sung

    IPC分类号： G11C7/00

    CPC分类号： G06F17/5031 ,  G06F2217/84 ,  G11C7/1066

    摘要： Systems and methods are disclosed for calibrating a Data Strobe (DQS) enable/disable signal and for tracking the timing of the DQS enable/disable signal with respect to changes in voltage and temperature (VT) in order to improve the timing margin of the DQS enable/disable signal in programmable devices using Double Data Rate (DDR) memory. In an exemplary embodiment, the system includes a gating circuit, a sampling circuit, and a delay chain tracking circuit. The gating circuit receives a DQS enable signal and a input DQS signal, calibrates the DQS enable signal based on an amount of delay, and outputs the calibrated DQS signal. The sampling circuit provides the amount of delay to the gating circuit based on a sampling clock. The delay chain tracking circuit maintains the timing of the calibrated DQS enable signal over a plurality of clock cycles based on the sampling clock and a leveling clock.

    摘要翻译： 公开了用于校准数据选通（DQS）使能/禁止信号的系统和方法，并且用于跟踪DQS使能/禁止信号相对于电压和温度（VT）的变化的定时，以便改善DQS的定时裕度 使用双倍数据速率（DDR）存储器在可编程器件中启用/禁用信号。 在示例性实施例中，该系统包括门控电路，采样电路和延迟链跟踪电路。 门控电路接收DQS使能信号和输入DQS信号，根据延迟量校准DQS使能信号，并输出校准的DQS信号。 采样电路基于采样时钟向门控电路提供延迟量。 延迟链跟踪电路基于采样时钟和调平时钟在多个时钟周期上维持校准的DQS使能信号的定时。

    Variation compensation circuitry for memory interface
    4.
    发明授权
    Variation compensation circuitry for memory interface 有权
    用于存储器接口的变差补偿电路

    公开(公告)号：US08565034B1

    公开(公告)日：2013-10-22

    申请号：US13249954

    申请日：2011-09-30

    申请人： Sean Shau-Tu Lu ,  Joseph Huang ,  Yan Chong ,  Pradeep Nagarajan ,  Chiakang Sung

    发明人： Sean Shau-Tu Lu ,  Joseph Huang ,  Yan Chong ,  Pradeep Nagarajan ,  Chiakang Sung

    IPC分类号： G11C7/00 ,  G11C7/22

    CPC分类号： G11C7/22 ,  G06F13/1689

    摘要： Integrated circuits may include memory interface circuitry operable to communicate with system memory. The memory interface circuitry may receive data and data strobe signals from system memory during read operations. The memory interface circuitry may include de-skew circuitry and dynamic variation compensation circuitry. The de-skew circuitry may be configured during calibration procedures to reduce skew between the data and data strobe signals. The dynamic variation compensation circuitry may be used in real time to compensate for variations in operating conditions. The dynamic variation compensation circuitry may include a phase generation circuit operable to generate data strobe signals having different phases, an edge detection circuit operable to detect leading/trailing edge failures, a control circuit operable to control a counter, and an adjustable delay circuit that is controlled by the counter and that is operable to properly position the data signal with respect to its corresponding data strobe signal.

    摘要翻译： 集成电路可以包括可操作以与系统存储器通信的存储器接口电路。 存储器接口电路可以在读取操作期间从系统存储器接收数据和数据选通信号。 存储器接口电路可以包括去偏移电路和动态变化补偿电路。 可以在校准过程期间配置去偏移电路，以减少数据和数据选通信号之间的偏差。 可以实时地使用动态变化补偿电路来补偿操作条件的变化。 动态变化补偿电路可以包括可产生具有不同相位的数据选通信号的相位产生电路，可操作以检测前沿/后沿故障的边缘检测电路，可操作以控制计数器的控制电路和可调延迟电路， 由计数器控制，并且可操作以相对于其对应的数据选通信号适当地定位数据信号。

    Techniques for providing multiple delay paths in a delay circuit
    5.
    发明授权
    Techniques for providing multiple delay paths in a delay circuit 有权
    在延迟电路中提供多个延迟路径的技术

    公开(公告)号：US08159277B1

    公开(公告)日：2012-04-17

    申请号：US13031129

    申请日：2011-02-18

    申请人： Pradeep Nagarajan ,  Yan Chong ,  Chiakang Sung ,  Joseph Huang

    发明人： Pradeep Nagarajan ,  Yan Chong ,  Chiakang Sung ,  Joseph Huang

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  H03K5/133 ,  H03K2005/00058

    摘要： A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuits includes variable delay blocks and fixed delay blocks that are coupled to form at least two delay paths for an input signal through the delay circuit to generate a delayed output signal. Delays of the variable delay blocks in the delay circuits vary based on the output signal of the phase detector. Each of the delay circuits reroutes the input signal through a different one of the delay paths to generate the delayed output signal based on the output signal of the phase detector during operation of the feedback loop circuit.

    摘要翻译： 反馈回路包括相位检测器和延迟电路。 相位检测器基于延迟周期信号产生输出信号。 延迟电路在延迟链中耦合，延迟链延迟了延迟的周期信号。 每个延迟电路包括可变延迟块和固定延迟块，其被耦合以形成用于通过延迟电路的输入信号的至少两个延迟路径以产生延迟的输出信号。 延迟电路中的可变延迟块的延迟基于相位检测器的输出信号而变化。 每个延迟电路通过不同的延迟路径重新路由输入信号，以在反馈回路电路的操作期间基于相位检测器的输出信号产生延迟的输出信号。

    Techniques for providing reduced duty cycle distortion
    6.
    发明授权
    Techniques for providing reduced duty cycle distortion 有权
    提供减少占空比失真的技术

    公开(公告)号：US08130016B2

    公开(公告)日：2012-03-06

    申请号：US12642502

    申请日：2009-12-18

    申请人： Pradeep Nagarajan ,  Yan Chong ,  Chiakang Sung ,  Joseph Huang

    发明人： Pradeep Nagarajan ,  Yan Chong ,  Chiakang Sung ,  Joseph Huang

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  H03K5/134 ,  H03K5/1565 ,  H03K2005/00065

    摘要： A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuits comprises variable delay blocks and fixed delay blocks that are coupled to form at least two delay paths for an input signal through the delay circuit to generate a delayed output signal. Delays of the variable delay blocks in the delay circuits vary based on the output signal of the phase detector. Each of the delay circuits reroutes the input signal through a different one of the delay paths to generate the delayed output signal based on the output signal of the phase detector during operation of the feedback loop circuit. Each of the variable delay blocks and the fixed delay blocks is inverting.

    摘要翻译： 反馈回路包括相位检测器和延迟电路。 相位检测器基于延迟周期信号产生输出信号。 延迟电路在延迟链中耦合，延迟链延迟了延迟的周期信号。 每个延迟电路包括可变延迟块和固定延迟块，其被耦合以形成用于通过延迟电路的输入信号的至少两个延迟路径以产生延迟的输出信号。 延迟电路中的可变延迟块的延迟基于相位检测器的输出信号而变化。 每个延迟电路通过不同的延迟路径重新路由输入信号，以在反馈回路电路的操作期间基于相位检测器的输出信号产生延迟的输出信号。 每个可变延迟块和固定延迟块都是反相的。

    DUTY CYCLE CORRECTION CIRCUIT FOR MEMORY INTERFACES IN INTEGRATED CIRCUITS
    7.
    发明申请
    DUTY CYCLE CORRECTION CIRCUIT FOR MEMORY INTERFACES IN INTEGRATED CIRCUITS 有权
    用于集成电路中的存储器接口的占空比校正电路

    公开(公告)号：US20110175657A1

    公开(公告)日：2011-07-21

    申请号：US12690064

    申请日：2010-01-19

    申请人： Yan Chong ,  Joseph Huang ,  Pradeep Nagarajan ,  Chiakang Sung

    发明人： Yan Chong ,  Joseph Huang ,  Pradeep Nagarajan ,  Chiakang Sung

    IPC分类号： H03K3/017

    CPC分类号： H03K5/1565 ,  H03K5/151 ,  H03K5/1534 ,  H03K2005/00019

    摘要： Circuits and a method for correcting duty cycle distortions in an integrated circuit (IC) are disclosed. The IC includes a splitter circuit that is coupled to receive a clock signal. The clock signal is split into two different clock signals. One of the clock signals is an inverted version of the other. A delay circuit is coupled to each of the clock signals. Each of the delay circuits generates a delayed version of the corresponding clock signal. A corrector circuit is coupled to receive both the delayed versions of the clock signals. The corrector circuit generates a clock output signal with a corrected duty cycle.

    摘要翻译： 公开了用于校正集成电路（IC）中的占空比失真的电路和方法。 IC包括被耦合以接收时钟信号的分离器电路。 时钟信号分为两个不同的时钟信号。 其中一个时钟信号是另一个的反转版本。 延迟电路耦合到每个时钟信号。 每个延迟电路产生相应时钟信号的延迟版本。 耦合校正器电路以接收时钟信号的延迟版本。 校正器电路产生具有校正占空比的时钟输出信号。

    Duty cycle correction circuit for memory interfaces in integrated circuits
    8.
    发明授权
    Duty cycle correction circuit for memory interfaces in integrated circuits 有权
    集成电路中存储器接口的占空比校正电路

    公开(公告)号：US08624647B2

    公开(公告)日：2014-01-07

    申请号：US12690064

    申请日：2010-01-19

    申请人： Yan Chong ,  Joseph Huang ,  Pradeep Nagarajan ,  Chiakang Sung

    发明人： Yan Chong ,  Joseph Huang ,  Pradeep Nagarajan ,  Chiakang Sung

    IPC分类号： H03K3/017

    CPC分类号： H03K5/1565 ,  H03K5/151 ,  H03K5/1534 ,  H03K2005/00019

    摘要： Circuits and a method for correcting duty cycle distortions in an integrated circuit (IC) are disclosed. The IC includes a splitter circuit that is coupled to receive a clock signal. The clock signal is split into two different clock signals. One of the clock signals is an inverted version of the other. A delay circuit is coupled to each of the clock signals. Each of the delay circuits generates a delayed version of the corresponding clock signal. A corrector circuit is coupled to receive both the delayed versions of the clock signals. The corrector circuit generates a clock output signal with a corrected duty cycle.

    摘要翻译： 公开了用于校正集成电路（IC）中的占空比失真的电路和方法。 IC包括被耦合以接收时钟信号的分离器电路。 时钟信号分为两个不同的时钟信号。 其中一个时钟信号是另一个的反转版本。 延迟电路耦合到每个时钟信号。 每个延迟电路产生相应时钟信号的延迟版本。 耦合校正器电路以接收时钟信号的延迟版本。 校正器电路产生具有校正占空比的时钟输出信号。

    Techniques for providing multiple delay paths in a delay circuit
    9.
    发明授权
    Techniques for providing multiple delay paths in a delay circuit 有权
    在延迟电路中提供多个延迟路径的技术

    公开(公告)号：US07893739B1

    公开(公告)日：2011-02-22

    申请号：US12549332

    申请日：2009-08-27

    申请人： Pradeep Nagarajan ,  Yan Chong ,  Chiakang Sung ,  Joseph Huang

    发明人： Pradeep Nagarajan ,  Yan Chong ,  Chiakang Sung ,  Joseph Huang

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  H03K5/133 ,  H03K2005/00058

    摘要： A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuits includes variable delay blocks and fixed delay blocks that are coupled to form at least two delay paths for an input signal through the delay circuit to generate a delayed output signal. Delays of the variable delay blocks in the delay circuits vary based on the output signal of the phase detector. Each of the delay circuits reroutes the input signal through a different one of the delay paths to generate the delayed output signal based on the output signal of the phase detector during operation of the feedback loop circuit.

    摘要翻译： 反馈回路包括相位检测器和延迟电路。 相位检测器基于延迟周期信号产生输出信号。 延迟电路在延迟链中耦合，延迟链延迟了延迟的周期信号。 每个延迟电路包括可变延迟块和固定延迟块，其被耦合以形成用于通过延迟电路的输入信号的至少两个延迟路径以产生延迟的输出信号。 延迟电路中的可变延迟块的延迟基于相位检测器的输出信号而变化。 每个延迟电路通过不同的一个延迟路径重新路由输入信号，以在反馈回路电路的操作期间基于相位检测器的输出信号产生延迟的输出信号。