公开(公告)号：US10346574B2

公开(公告)日：2019-07-09

申请号：US15625754

申请日：2017-06-16

Applicant: QUALCOMM Incorporated

Inventor： Rajesh Arimilli ,  Sabyasachi Sarkar ,  Gaurav Arya

IPC: G06F17/50 ,  H01L27/00 ,  H01L21/768 ,  H01L27/02 ,  H01L27/118

Abstract: An IC includes a first IC portion and a second IC portion. The IC includes a first set of standard cells in the first IC portion. The IC includes a plurality of memory cells and a second set of standard cells in the second IC portion. The second set of standard cells is located in channels between the memory cells. The IC further includes a plurality of GDHS cells in the first IC portion. The GDHS cells are configured to switch power on and to switch power off to the first set of standard cells. The IC further includes a plurality of CHS cells in the first IC portion. The CHS cells are configured to switch power on and to switch power off to the second set of standard cells in the second IC portion.