公开(公告)号：US20250086114A1

公开(公告)日：2025-03-13

申请号：US18466171

申请日：2023-09-13

Applicant: QUALCOMM Incorporated

Inventor： Karunakar Reddy BASIREDDY ,  George PATSILARAS ,  Vivekanandan NAVEEN

IPC: G06F12/0871

Abstract: A device includes a system cache accessible to a central processing unit (CPU) sub-system. The system cache includes a CPU portion allocated to the CPU sub-system. The device also includes a cache allocation governor that is configured to obtain a performance metric associated with at least one of the system cache or the CPU sub-system. The cache allocation governor is also configured to, based on the performance metric satisfying a cache adjustment criterion, adjust a size of the CPU portion.