公开(公告)号：US20240275348A1

公开(公告)日：2024-08-15

申请号：US18110295

申请日：2023-02-15

Applicant: QUALCOMM Incorporated

Inventor： Marco VIGILANTE ,  Yunliang ZHU

IPC: H03F3/72 ,  H04B1/04

CPC classification number: H03F3/72 ,  H04B1/04 ,  H04B2001/0408

Abstract: A two-stage circuit includes a differential-to-single-ended first stage with a differential pair of transistors. The first stage includes a current mirror including a diode-connected transistor having an RC circuit coupled to a drain of the diode-connected transistor. The current mirror is configured to mirror a power supply noise current conducted by the RC circuit through a first stage output terminal to a gate of an output transistor in a second stage of the two-stage circuit.

公开(公告)号：US20160079985A1

公开(公告)日：2016-03-17

申请号：US14487906

申请日：2014-09-16

Applicant: QUALCOMM Incorporated

Inventor： Yunliang ZHU ,  Kevin Hsi-huai WANG ,  Rajagopalan RANGARAJAN

IPC: H03K23/54 ,  H04L27/12 ,  H03K21/10

CPC classification number: H03K23/544 ,  H03K21/10

Abstract: Certain aspects of the present disclosure provide techniques and apparatus for generating in-phase and quadrature (I/Q) local oscillator (LO) signals that may be synthesized using signals output from a divide-by-odd-number frequency divider (e.g., Div3 or Div5). This may be accomplished by deriving each period of the LO signal from a selected output signal of the frequency divider such that the average phase over multiple LO periods yields desired I/Q LO signals. This operation may save current because a phase interpolation circuit need not be used and moreover, provide I/Q LO signals having equal gain. Certain aspects of the present disclosure also provide a “dummy” LO signal, which may be used to in conjunction with a “dummy load” to present constant load impedance to a low noise amplifier (LNA) during time gaps (periods of an oscillating signal input to the frequency divider) in which the I/Q LO signals are all off.

Abstract translation: 本公开的某些方面提供用于产生可以使用从奇数分频器（例如Div3）输出的信号来合成的同相和正交（I / Q）本地振荡器（LO）信号的技术和装置 或Div5）。 这可以通过从分频器的选定的输出信号导出LO信号的每个周期来实现，使得多个LO周期上的平均相位产生期望的I / Q LO信号。 该操作可以节省电流，因为不需要使用相位插值电路，而且提供具有相等增益的I / Q LO信号。 本公开的某些方面还提供了一种“虚拟”LO信号，其可以与“虚拟负载”结合使用以在时间间隔期间向低噪声放大器（LNA）提供恒定负载阻抗（振荡信号的周期 输入到分频器），其中I / Q LO信号全部关闭。