公开(公告)号：US20150149810A1

公开(公告)日：2015-05-28

申请号：US14139704

申请日：2013-12-23

Applicant: Qualcomm Incorporated

Inventor： DHAMIM PACKER ALI ,  TOM C. WANG ,  SHA LIU ,  SREENIVASULU REDDY CHALAMCHARLA

IPC: G06F11/14

CPC classification number: G06F11/1441 ,  G06F11/1492 ,  G06F11/2236

Abstract: A power management mechanism maintains power to a processor and an integrated memory. Read-only logic and a cache are also provided. At power on, the read-only logic configures the cache as an internal memory and loads executable instructions in the cache. A copy of the executable instructions is stored in the internal memory. A branch instruction is also stored. Thereafter, the processor uses the copy of the executable instructions and present status information. The processor is programmed to issue a reset signal when a failure is detected. The read-only logic responds to the reset signal by going to the branch instruction in the internal memory, which directs the processor to use the copy of the executable instructions and status information in the internal memory circuit. The operating state is restored and the processor is instructed to execute the next instruction in the copy of executable instructions.

Abstract translation: 电源管理机构维持处理器和集成存储器的电源。 还提供只读逻辑和缓存。 上电时，只读逻辑将高速缓存配置为内部存储器，并在缓存中加载可执行指令。 可执行指令的副本存储在内部存储器中。 还存储分支指令。 此后，处理器使用可执行指令的副本并呈现状态信息。 处理器被编程为在检测到故障时发出复位信号。 只读逻辑通过转到内部存储器中的分支指令来响应复位信号，这引导处理器使用内部存储器电路中的可执行指令和状态信息的副本。 恢复操作状态，并指示处理器执行可执行指令副本中的下一条指令。