公开(公告)号：US3634769A

公开(公告)日：1972-01-11

申请号：US3634769D

申请日：1969-12-12

Applicant: RELEX CORP

Inventor： SLEATER ROLAND G ,  REED CHARLES G

IPC: G05B19/07 ,  G06F1/14 ,  H03K17/00 ,  H03K17/26

CPC classification number: H03K17/002 ,  G05B19/07 ,  G05B2219/25411 ,  G06F1/14

Abstract: A gating circuit for sequentially initiating a plurality of different processes or events in accordance with a predetermined preferential sequence of activation. A plurality of gates are provided, each of which receives an independent input signal for initiating the corresponding process or event. The output signal of each gate circuit is fed back to all of the other gate circuits as an inhibiting signal to prevent any two of the gates from being activated at the same time. The inhibiting signals are applied to the other gates through a plurality of different delay lines which establish a preferential time sequence of gate activation. When one gate has been activated, it inhibits all of the other gates until the corresponding process or event has been completed, at which time the inhibiting signal to the other gates is removed. Due to the difference in delay time, however, the removal of the inhibiting signal occurs in a time sequence which establishes a preferential sequence of gate activation for the remaining gates.