公开(公告)号：US20200265876A1

公开(公告)日：2020-08-20

申请号：US16802073

申请日：2020-02-26

Applicant: Rambus Inc.

Inventor： MICHAEL L. TAKEFMAN ,  MAHER AMER ,  CLAUS REITLINGSHOEFER ,  RICCARDO BADALONE

IPC: G11C7/10 ,  G11C5/04

Abstract: A system and method for providing a configurable timing control of a memory system is disclosed. In one embodiment, the system has a first interface to receive a DIMM clock and configuration information, a second interface to a first data bus, and a third interface to a second data bus. The system further has a plurality of flip-flops, a multiplexor coupled to the plurality of flip-flops, a first control block for controlling to hold an input data within the plurality of flip-flops, and a second control block for controlling a timing of an output data from the plurality of flip-flops via the multiplexor with a programmable delay. The input data is received via the second interface. The programmable delay is received via the first interface. The output data is sent out with the timing delay via the third interface.

公开(公告)号：US20190043541A1

公开(公告)日：2019-02-07

申请号：US15907390

申请日：2018-02-28

Applicant: Rambus Inc

Inventor： MICHAEL L. TAKEFMAN ,  MAHER AMER ,  CLAUS REITLINGSHOEFER ,  RICCARDO BADALONE

IPC: G11C7/10 ,  G11C8/18

Abstract: A system and method for providing a configurable timing control of a memory system is disclosed. In one embodiment, the system has a first interface to receive a DIMM clock and configuration information, a second interface to a first data bus, and a third interface to a second data bus. The system further has a plurality of flip-flops, a multiplexor coupled to the plurality of flip-flops, a first control block for controlling to hold an input data within the plurality of flip-flops, and a second control block for controlling a timing of an output data from the plurality of flip-flops via the multiplexor with a programmable delay. The input data is received via the second interface. The programmable delay is received via the first interface. The output data is sent out with the timing delay via the third interface,